APEX 20K Programmable Logic Device Family Data Sheet
Table 38 through 41 show APEX 20KE LE, ESB, routing, and functional
timing microparameters for the fMAX timing model.
Table 38. APEX 20KE LE Timing Microparameters
Symbol
Parameter
t
t
t
t
LE register setup time before clock
LE register hold time after clock
LE register clock-to-output delay
LUT delay for data-in to data-out
SU
H
CO
LUT
Table 39. APEX 20KE ESB Timing Microparameters
Symbol
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
ESB Asynchronous read cycle time
ESBARC
ESB Synchronous read cycle time
ESBSRC
ESB Asynchronous write cycle time
ESBAWC
ESB Synchronous write cycle time
ESBSWC
ESB write address setup time with respect to WE
ESB write address hold time with respect to WE
ESB data setup time with respect to WE
ESB data hold time with respect to WE
ESBWASU
ESBWAH
ESBWDSU
ESBWDH
ESB read address setup time with respect to RE
ESB read address hold time with respect to RE
ESB WE setup time before clock when using input register
ESB data setup time before clock when using input register
ESBRASU
ESBRAH
ESBWESU
ESBDATASU
ESBWADDRSU
ESB write address setup time before clock when using input
registers
t
ESB read address setup time before clock when using input
registers
ESBRADDRSU
t
t
t
t
t
t
ESB clock-to-output delay when using output registers
ESB clock-to-output delay without output registers
ESB data-in to data-out delay for RAM mode
ESB Macrocell input to non-registered output
ESB Macrocell register setup time before clock
ESB Macrocell register clock-to-output delay
ESBDATACO1
ESBDATACO2
ESBDD
PD
PTERMSU
PTERMCO
Altera Corporation
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