APEX 20K Programmable Logic Device Family Data Sheet
Figure 39. ESB Synchronous Timing Waveforms
ESB Synchronous Read
WE
Rdaddress
CLK
a0
a1
a2
a3
tESBDATASU
tESBDATAH
tESBARC
tESBDATACO2
Data-Out
d1
d2
ESB Synchronous Write (ESB Output Registers Used)
WE
din1
din2
din3
a3
Data-In
a0
a1
a2
a2
Wraddress
tESBWESU
tESBDATAH
tESBWEH
tESBDATASU
CLK
tESBDATACO1
tESBSWC
dout0
dout1
din1
din2
din3
din2
Data-Out
Figure 40 shows the timing model for bidirectional I/ O pin timing.
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Altera Corporation