APEX 20K Programmable Logic Device Family Data Sheet
Table 35. APEX 20K fMAX Timing Parameters
(Part 2 of 2)
Parameter
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
ESB data-in to data-out delay for RAM mode
ESB macrocell input to non-registered output
ESBDD
PD
ESB macrocell register setup time before clock
ESB macrocell register clock-to-output delay
Fanout delay using local interconnect
Fanout delay using MegaLab Interconnect
Fanout delay using FastTrack Interconnect
Minimum clock high time from clock pin
Minimum clock low time from clock pin
LE clear pulse width
PTERMSU
PTERMCO
F1-4
F5-20
F20+
CH
CL
CLRP
PREP
ESBCH
ESBCL
ESBWP
ESBRP
LE preset pulse width
Clock high time
Clock low time
Write pulse width
Read pulse width
Tables 36 and 37 describe APEX 20K external timing parameters.
Table 36. APEX 20K External Timing Parameters
Note (1)
Symbol
Clock Parameter
Conditions
t
t
t
Setup time with global clock at IOE register
Hold time with global clock at IOE register
INSU
INH
Clock-to-output delay with global clock at IOE register
OUTCO
Table 37. APEX 20K External Bidirectional Timing Parameters
Symbol Parameter
Note (1)
Condition
t
t
t
Setup time for bidirectional pins with global clock at same-row or same-
column LE register
INSUBIDIR
Hold time for bidirectional pins with global clock at same-row or same-
column LE register
INHBIDIR
Clock-to-output delay for bidirectional pins with global clock at IOE
register
C1 = 35 pF
OUTCOBIDIR
t
t
Synchronous IOE output buffer disable delay
C1 = 35 pF
C1 = 35 pF
XZBIDIR
ZXBIDIR
Synchronous IOE output buffer enable delay, slow slew rate = off
Note to tables:
(1) These timing parameters are sample-tested only.
76
Altera Corporation
ETC [ ETC ]
