APEX 20K Programmable Logic Device Family Data Sheet
Table 43. APEX 20KE External Bidirectional Timing Parameters
Symbol Parameter
Note (1)
Condition
t
t
t
Setup time for bi-directional pins with global clock at LAB adjacent Input
Register
INSUBIDIR
Hold time for bi-directional pins with global clock at LabB adjacent Input
Register
INHBIDIR
Clock-to-output delay for bi-directional pins with global clock at IOE output
register
C1 = 35 pF
OUTCOBIDIR
t
t
t
Synchronous Output Enable Register to output buffer disable delay
Synchronous Output Enable Register output buffer enable delay
C1 = 35 pF
C1 = 35 pF
XZBIDIR
ZXBIDIR
Setup time for bi-directional pins with PLL clock at LAB adjacent Input
Register
INSUBIDIRPLL
t
t
t
t
Hold time for bi-directional pins with PLL clock at LAB adjacent Input
Register
INHBIDIRPLL
OUTCOBIDIRPLL
XZBIDIRPLL
Clock-to-output delay for bi-directional pins with PLL clock at IOE output
register
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
Synchronous Output Enable Register to output buffer disable delay with
PLL
Synchronous Output Enable Register output buffer enable delay with PLL
ZXBIDIRPLL
Note to tables:
(1) These timing parameters are sample-tested only.
Altera Corporation
79
ETC [ ETC ]
