APEX 20K Programmable Logic Device Family Data Sheet
All specifications are always representative of worst-case supply voltage
and junction temperature conditions. All output-pin-timing specifications
are reported for maximum driver strength.
Figure 36 shows the fMAX timing model for APEX 20K devices.
Figure 36. APEX 20K fMAX Timing Model
LE
tSU
Routing Delay
tH
tF1—4
tF5—20
tF20+
tCO
tLUT
ESB
tESBRC
tESBWC
tESBWESU
tESBDATASU
tESBADDRSU
tESBDATACO1
tESBDATACO2
tESBDD
tPD
tPTERMSU
tPTERMCO
Figure 37 shows the fMAX timing model for APEX 20KE devices. These
parameters can be used to estimate fMAX for multipule levels of logic.
Quartus II software timing analysis should be used for more accurate
timing information.
Altera Corporation
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ETC [ ETC ]
