RTL8201BL
6. Register Descriptions
This section will describe definitions and usage for each of the registers available in the RTL8201BL.
6.1 Register 0 Basic Mode Control Register
Address
Name
Description/Usage
Default/Attribute
0:<15>
Reset
This bit sets the status and control registers of the
PHY in a default state. This bit is self-clearing.
1 = software reset
0, RW
0, RW
1, RW
0 = normal operation
0:<14>
0:<13>
Loopback
Spd_Set
This bit enables loopback of transmit data nibbles
TXD<3:0> to the receive data path.
1 = enable loopback
0 = normal operation
This bit sets the network speed.
1 = 100Mbps
0 = 10Mbps
When 100Base-FX mode is enabled, this bit=1 and is
read only.
0:<12>
Auto
Negotiation
Enable
This bit enables/disables the Nway auto-negotiation
function.
1, RW
1 = enable auto-negotiation; bits 0:<13> and 0:<8>
will be ignored.
0 = disable auto-negotiation; bits 0:<13> and 0:<8>
will determine the link speed and the data transfer
mode, respectively.
When 100Base-FX mode is enabled, this bit=0 and is
read only.
0:<11>
Power Down This bit turns down the power of the PHY chip
including internal crystal oscillator circuit. The MDC,
MDIO is still alive for accessing the MAC.
1 = power down
0, RW
0 = normal operation
0:<10>
0:<9>
Reserved
Restart Auto This bits allows the Nway auto-negotiation function
0, RW
1, RW
Negotiation
to be reset.
1 = re-start auto-negotiation
0 = normal operation
0:<8>
Duplex Mode This bit sets the duplex mode if auto negotiation is
disabled (bit 0:<12>=0)
1 = full duplex
0 = half duplex
After completing auto negotiation, this bit will reflect
the duplex status.(1: Full duplex, 0: Half duplex)
When 100Base-FX mode is enabled, this bit can be
set through the MDC/MDIO SMI interface or
DUPLEX pin.
0:<7:0>
Reserved
2002-03-29
Rev.1.2
8
ETC [ ETC ]
