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RTL8201BL 参数 Datasheet PDF下载

RTL8201BL图片预览
型号: RTL8201BL
PDF下载: 下载PDF文件 查看货源
内容描述: REALTEK单片单端口10 / 100M快速以太网PHYCEIVER RTL8201BL [REALTEK SINGLE CHIP SINGLE PORT 10/100M FAST ETHERNET PHYCEIVER RTL8201BL]
分类和应用: LTE以太网局域网(LAN)标准以太网:16GBASE-T
文件页数/大小: 29 页 / 335 K
品牌: ETC [ ETC ]
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RTL8201BL  
5. Pin Description  
LI: Latched Input in power up or reset  
I/O: Bi-directional input and output  
O: Output  
I: Input  
P: Power  
5.1 100 Mbps MII & PCS Interface  
Symbol  
Type  
Pin No.  
Description  
TXC  
O
7
Transmit Clock: This pin provides a continuous clock as a timing reference  
for TXD[3:0] and TXEN.  
TXEN  
TXD[3:0]  
RXC  
I
I
2
3, 4, 5, 6  
16  
Transmit Enable: The input signal indicates the presence of a valid nibble  
data on TXD[3:0].  
Transmit Data: MAC will source TXD[0..3] synchronous with TXC when  
TXEN is asserted.  
Receive Clock: This pin provides a continuous clock reference for RXDV  
and RXD[0..3] signals. RXC is 25MHz in the 100Mbps mode and 2.5Mhz in  
the 10Mbps mode.  
O
COL  
O
O
O
1
23  
22  
Collision Detected: COL is asserted high when a collision is detected on the media.  
Carrier Sense: This pin’s signal is asserted high if the media is not in IDEL state.  
Receive Data Valid: This pin’s signal is asserted high when received data is  
present on the RXD[3:0] lines; the signal is deasserted at the end of the  
packet. The signal is valid on the rising of the RXC.  
CRS  
RXDV  
RXD[3:0]  
O
18, 19, 20, 21  
24  
Receive Data: These are the four parallel receive data lines aligned on the  
nibble boundaries driven synchronously to the RXC for reception by the  
external physical unit (PHY).  
RXER/  
FXEN  
O/LI  
Receive error: if any 5B decode error occurs, such as invalid J/K, T/R,  
invalid symbol, this pin will go high.  
Fiber/UTP Enable: During power on reset, this pin status is latched to  
determine at which media mode to operate:  
1: Fiber mode  
0: UTP mode  
An internal weak pull low resistor, sets this to the default of UTP mode. It is  
possible to use an external 5.1Kpull high resistor to enable fiber mode.  
After power on, the pin operates as the Receive Error pin.  
Management Data Clock: This pin provides a clock synchronous to MDIO,  
which may be asynchronous to the transmit TXC and receive RXC clocks.  
The clock rate can be up to 2.5MHz.  
MDC  
I
25  
MDIO  
I/O  
26  
Management Data Input/Output: This pin provides the bi-directional  
signal used to transfer management information.  
5.2 SNI (Serial Network Interface): 10Mbps only  
Symbol  
Type  
Pin No.  
Description  
COL  
O
1
21  
23  
16  
6
Collision Detect  
Received Serial Data  
Carrier Sense  
Receive Clock: Resolved from received data  
Transmit Serial Data  
Transmit Clock: Generate by PHY  
Transmit Enable: For MAC to indicate transmit operation  
RXD0  
CRS  
O
O
RXC  
O
TXD0  
TXC  
I
O
7
TXEN  
I
2
2002-03-29  
Rev.1.2  
5