RTL8201BL
6.9 Register 17 Loopback, Bypass, Receiver Error Mask
Register(LBREMR)
Address
17:<15>
17:<14>
Name
RPTR
Description/Usage
Set to 1 to put the RTL8201BL into repeater mode
Assertion of this bit allows bypassing of the 4B/5B &
5B/4B encoder.
Default/Attribute
0, RW
BP_4B5B
0, RW
17:<13>
BP_SCR
Assertion of this bit allows bypassing of the
scrambler/descrambler.
0, RW
17:<12>
17:<11>
LDPS
AnalogOFF
Set to 1 to enable Link Down Power Saving mode
Set to 1 to power down analog function of transmitter
and receiver.
0, RW
0, RW
17:<10>
17:<9:8>
DetectLength Detect length OK indication. Assert low to indicate
detect length OK.
LB<1:0>
0, RO
LB<1:0> are register bits for loopback control as
defined below:
<0, 0>, RW
1) 0 0 for normal mode;
2) 0 1 for PHY loopback;
3) 1 0 for twister loopback
17:<7>
F_Link_100
Used to logic force good link in 100Mbps for
diagnostic purposes.
1, RW
17:<6:5>
17:<4>
Reserved
CODE_err
Assertion of this bit causes a code error detection to
be reported.
0, RW
0, RW
0, RW
0, RW
0, RW
17:<3>
17:<2>
17:<1>
17:<0>
PME_err
LINK_err
PKT_err
RWPara
Assertion of this bit causes a pre-mature end error
detection to be reported.
Assertion of this bit causes a link error detection to be
reported.
Assertion of this bit causes a detection of packet
errors due to 722 ms time-out to be reported.
Parameter access enable, set 1 to access register
20~24
6.10 Register 18 RX_ER Counter(REC)
Address
18:<15:0>
Name
RXERCNT
Description/Usage
This 16-bit counter increments by 1 for each valid
packet received.
Default/Attribute
H’[0000],
RW
6.11 Register 19 10Mbps Network Interface Configuration Register
Address
19:<15:6>
19:<5>
Name
Reserved
LD
Description/Usage
Default/Attribute
This bit is the active low TPI link disable signal.
When low TPIstilltransmit link pulses and TPI stays
in good link state.
1, RW
19:<4:2>
19:<1>
19:<0>
Reserved
HBEN
JBEN
Heart beat enable
1 = enable jabber function
0 = disable jabber function
1, RW
1, RW
2002-03-29
Rev.1.2
12
ETC [ ETC ]
