RTL8100C & RTL8100CL
Datasheet
Bit
R/W
Symbol
Description
2
R
CRC
Cyclic Redundancy Check (CRC) Error.
When set, indicates that a CRC error occurred on the received
packet.
1
0
R
R
FAE
Frame Alignment Error.
When set, indicates that a frame alignment error occurred on this
received packet.
ROK
Receive OK.
When set, indicates that a good packet was received.
5.10. Transmit Status Register
(TSD0-3)(Offset 0010h-001Fh, R/W)
The read-only bits (CRS, TABT, OWC, CDH, NCC3-0, TOK, TUN) will be cleared by the RTL8100C(L)
when the Transmit Byte Count (bits 12-0) in the corresponding Tx descriptor is written. It is not affected
when software writes to these bits. These registers are only permitted to be written via double-word access.
After a software reset, all bits except OWN bit are reset to 0.
Table 10. Transmit Status Register
Bit
R/W
Symbol
Description
31
R
CRS
Carrier Sense Lost.
This bit is set to 1 when the carrier is lost during transmission of a
packet.
30
29
28
R
R
R
TABT
OWC
CDH
Transmit Abort.
This bit is set to 1 if the transmission of a packet was aborted. This bit
is read only, writing to this bit is not affected.
Out of Window Collision.
This bit is set to 1 if the RTL8100C(L) encountered an ‘out of window’
collision during the transmission of a packet.
CD HeartBeat.
The NIC watches for a collision signal (i.e., CD Heartbeat signal)
during the first 6.4µs of the InterFrame Gap following a
transmission. This bit is set if the transceiver fails to send this signal.
This bit is cleared in 100Mbps mode.
27-24
R
NCC3-0
Number of Collision Count.
Indicates the number of collisions encountered during the
transmission of a packet.
23-22
21-16
-
-
Reserved.
Early Tx Threshold.
R/W
ERTXTH5-0
Specifies the threshold level in the Tx FIFO to begin the
transmission. When the byte count of the data in the Tx FIFO reaches
this level, (or the FIFO contains at least one complete packet) the
RTL8100C(L) will transmit this packet.
000000 = 8 bytes
These fields count from 000001 to 111111 in units of 32 bytes.
This threshold must be prevented from exceeding 2k bytes.
Single-Chip Fast Ethernet Controller
13
Track ID: JATR-1076-21 Rev. 1.06
ETC [ ETC ]
