欢迎访问ic37.com |
会员登录 免费注册
发布采购

RTL8100CL 参数 Datasheet PDF下载

RTL8100CL图片预览
型号: RTL8100CL
PDF下载: 下载PDF文件 查看货源
内容描述: 电源管理单芯片快速以太网控制器 [SINGLE-CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT]
分类和应用: 外围集成电路控制器LTE局域网以太网以太网:16GBASE-T
文件页数/大小: 73 页 / 652 K
品牌: ETC [ ETC ]
 浏览型号RTL8100CL的Datasheet PDF文件第17页浏览型号RTL8100CL的Datasheet PDF文件第18页浏览型号RTL8100CL的Datasheet PDF文件第19页浏览型号RTL8100CL的Datasheet PDF文件第20页浏览型号RTL8100CL的Datasheet PDF文件第22页浏览型号RTL8100CL的Datasheet PDF文件第23页浏览型号RTL8100CL的Datasheet PDF文件第24页浏览型号RTL8100CL的Datasheet PDF文件第25页  
RTL8100C & RTL8100CL  
Datasheet  
Bit  
R/W  
Symbol  
Description  
2
R
CRC  
Cyclic Redundancy Check (CRC) Error.  
When set, indicates that a CRC error occurred on the received  
packet.  
1
0
R
R
FAE  
Frame Alignment Error.  
When set, indicates that a frame alignment error occurred on this  
received packet.  
ROK  
Receive OK.  
When set, indicates that a good packet was received.  
5.10. Transmit Status Register  
(TSD0-3)(Offset 0010h-001Fh, R/W)  
The read-only bits (CRS, TABT, OWC, CDH, NCC3-0, TOK, TUN) will be cleared by the RTL8100C(L)  
when the Transmit Byte Count (bits 12-0) in the corresponding Tx descriptor is written. It is not affected  
when software writes to these bits. These registers are only permitted to be written via double-word access.  
After a software reset, all bits except OWN bit are reset to 0.  
Table 10. Transmit Status Register  
Bit  
R/W  
Symbol  
Description  
31  
R
CRS  
Carrier Sense Lost.  
This bit is set to 1 when the carrier is lost during transmission of a  
packet.  
30  
29  
28  
R
R
R
TABT  
OWC  
CDH  
Transmit Abort.  
This bit is set to 1 if the transmission of a packet was aborted. This bit  
is read only, writing to this bit is not affected.  
Out of Window Collision.  
This bit is set to 1 if the RTL8100C(L) encountered an ‘out of window’  
collision during the transmission of a packet.  
CD HeartBeat.  
The NIC watches for a collision signal (i.e., CD Heartbeat signal)  
during the first 6.4µs of the InterFrame Gap following a  
transmission. This bit is set if the transceiver fails to send this signal.  
This bit is cleared in 100Mbps mode.  
27-24  
R
NCC3-0  
Number of Collision Count.  
Indicates the number of collisions encountered during the  
transmission of a packet.  
23-22  
21-16  
-
-
Reserved.  
Early Tx Threshold.  
R/W  
ERTXTH5-0  
Specifies the threshold level in the Tx FIFO to begin the  
transmission. When the byte count of the data in the Tx FIFO reaches  
this level, (or the FIFO contains at least one complete packet) the  
RTL8100C(L) will transmit this packet.  
000000 = 8 bytes  
These fields count from 000001 to 111111 in units of 32 bytes.  
This threshold must be prevented from exceeding 2k bytes.  
Single-Chip Fast Ethernet Controller  
13  
Track ID: JATR-1076-21 Rev. 1.06