欢迎访问ic37.com |
会员登录 免费注册
发布采购

RTL8100CL 参数 Datasheet PDF下载

RTL8100CL图片预览
型号: RTL8100CL
PDF下载: 下载PDF文件 查看货源
内容描述: 电源管理单芯片快速以太网控制器 [SINGLE-CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT]
分类和应用: 外围集成电路控制器LTE局域网以太网以太网:16GBASE-T
文件页数/大小: 73 页 / 652 K
品牌: ETC [ ETC ]
 浏览型号RTL8100CL的Datasheet PDF文件第20页浏览型号RTL8100CL的Datasheet PDF文件第21页浏览型号RTL8100CL的Datasheet PDF文件第22页浏览型号RTL8100CL的Datasheet PDF文件第23页浏览型号RTL8100CL的Datasheet PDF文件第25页浏览型号RTL8100CL的Datasheet PDF文件第26页浏览型号RTL8100CL的Datasheet PDF文件第27页浏览型号RTL8100CL的Datasheet PDF文件第28页  
RTL8100C & RTL8100CL  
Datasheet  
Bit  
R/W  
Symbol  
Description  
13  
R/W  
LenChg  
Cable Length Change Interrupt.  
1: Enable  
0: Disable  
12-7  
6
-
-
Reserved.  
Rx FIFO Overflow Interrupt.  
1: Enable  
R/W  
FOVW  
0: Disable  
5
4
3
2
1
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
PUN/LinkChg  
RXOVW  
TER  
Packet Underrun/Link Change Interrupt.  
1: Enable  
0: Disable  
Rx Buffer Overflow Interrupt.  
1: Enable  
0: Disable  
Transmit Error Interrupt.  
1: Enable  
0: Disable  
Transmit OK Interrupt.  
1: Enable  
0: Disable  
Receive Error Interrupt.  
1: Enable  
0: Disable  
Receive OK Interrupt.  
1: Enable  
TOK  
RER  
ROK  
0: Disable  
5.14. Interrupt Status Register (Offset 003Eh-003Fh, R/W)  
This register indicates the source of an interrupt when the INTA pin goes active. Enabling the  
corresponding bits in the Interrupt Mask Register (IMR) allows bits in this register to produce an interrupt.  
When an interrupt is active, one or more bits in this register are set to 1. The interrupt Status Register  
reflects all current pending interrupts, regardless of the state of the corresponding mask bit in the IMR.  
Reading the ISR clears all interrupts. Writing to the ISR has no effect.  
Table 14. Interrupt Status Register  
Bit  
R/W  
Symbol  
Description  
15  
R/W  
SERR  
System Error.  
Set to 1 when the RTL8100C(L) signals a system error on the PCI  
bus.  
14  
R/W  
TimeOut  
Time Out.  
Set to 1 when the TCTR register reaches the value of the TimerInt  
register.  
13  
R/W  
-
LenChg  
-
Cable Length Change.  
Cable length is changed after Receiver is enabled.  
Reserved.  
12 - 7  
Single-Chip Fast Ethernet Controller  
16  
Track ID: JATR-1076-21 Rev. 1.06