RTL8100C & RTL8100CL
Datasheet
Bit
R/W
Symbol
Description
13
R/W
LenChg
Cable Length Change Interrupt.
1: Enable
0: Disable
12-7
6
-
-
Reserved.
Rx FIFO Overflow Interrupt.
1: Enable
R/W
FOVW
0: Disable
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
PUN/LinkChg
RXOVW
TER
Packet Underrun/Link Change Interrupt.
1: Enable
0: Disable
Rx Buffer Overflow Interrupt.
1: Enable
0: Disable
Transmit Error Interrupt.
1: Enable
0: Disable
Transmit OK Interrupt.
1: Enable
0: Disable
Receive Error Interrupt.
1: Enable
0: Disable
Receive OK Interrupt.
1: Enable
TOK
RER
ROK
0: Disable
5.14. Interrupt Status Register (Offset 003Eh-003Fh, R/W)
This register indicates the source of an interrupt when the INTA pin goes active. Enabling the
corresponding bits in the Interrupt Mask Register (IMR) allows bits in this register to produce an interrupt.
When an interrupt is active, one or more bits in this register are set to 1. The interrupt Status Register
reflects all current pending interrupts, regardless of the state of the corresponding mask bit in the IMR.
Reading the ISR clears all interrupts. Writing to the ISR has no effect.
Table 14. Interrupt Status Register
Bit
R/W
Symbol
Description
15
R/W
SERR
System Error.
Set to 1 when the RTL8100C(L) signals a system error on the PCI
bus.
14
R/W
TimeOut
Time Out.
Set to 1 when the TCTR register reaches the value of the TimerInt
register.
13
R/W
-
LenChg
-
Cable Length Change.
Cable length is changed after Receiver is enabled.
Reserved.
12 - 7
Single-Chip Fast Ethernet Controller
16
Track ID: JATR-1076-21 Rev. 1.06
ETC [ ETC ]
