RTL8100C & RTL8100CL
Datasheet
Offset
0089h
008Ah
008Bh
008Ch–0093h
0094h–009Bh
009Ch–00A3h
00A4h–00ABh
00ACh–00B3h
00B4h–00BBh
00BCh–00C3h
00C4h–00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h-00D7h
00D8h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
Tag
CRC5
CRC6
CRC7
Description
Power Management CRC register 5 for wakeup frame 5.
Power Management CRC register 6 for wakeup frame 6.
Power Management CRC register 7 for wakeup frame 7.
Power Management Wakeup frame 0 (64-bit).
Power Management Wakeup frame 1 (64-bit).
Power Management Wakeup frame 2 (64-bit).
Power Management Wakeup frame 3 (64-bit).
Power Management Wakeup frame 4 (64-bit).
Power Management Wakeup frame 5 (64-bit).
Power Management Wakeup frame 6 (64-bit).
Power Management Wakeup frame 7 (64-bit).
LSB of the mask byte of wakeup frame 0 within offset 12 to 75.
LSB of the mask byte of wakeup frame 1 within offset 12 to 75.
LSB of the mask byte of wakeup frame 2 within offset 12 to 75.
LSB of the mask byte of wakeup frame 3 within offset 12 to 75.
LSB of the mask byte of wakeup frame 4 within offset 12 to 75.
LSB of the mask byte of wakeup frame 5 within offset 12 to 75.
LSB of the mask byte of wakeup frame 6 within offset 12 to 75.
LSB of the mask byte of wakeup frame 7 within offset 12 to 75.
Reserved.
Wakeup0
Wakeup1
Wakeup2
Wakeup3
Wakeup4
Wakeup5
Wakeup6
Wakeup7
LSBCRC0
LSBCRC1
LSBCRC2
LSBCRC3
LSBCRC4
LSBCRC5
LSBCRC6
LSBCRC7
-
R/W
-
Config5
-
Configuration register 5.
Reserved.
00D9h-00FFh
5.9. Receive Status Register in RX Packet Header
Table 9. Receive Status Register in RX Packet Header
Bit
R/W
Symbol
Description
15
R
MAR
Multicast Address Received.
This bit set to 1 indicates that a multicast packet has been received.
Physical Address Matched.
This bit set to 1 indicates that the destination address of this packet
matches the value written in ID registers.
Broadcast Address Received.
14
13
R
R
PAM
BAR
This bit set to 1 indicates that a broadcast packet is received. BAR,
MAR bit will not be set simultaneously.
Reserved.
Invalid Symbol Error (100Base-TX only).
This bit set to 1 indicates that an invalid symbol was encountered during
the reception of this packet.
12-6
5
-
R
-
ISE
4
3
R
R
RUNT
LONG
Runt Packet Received.
This bit set to 1 indicates that the received packet length is smaller than
64 bytes ( i.e. media header + data + CRC < 64 bytes )
Long Packet.
This bit set to 1 indicates that the size of the received packet exceeds
4k bytes.
Single-Chip Fast Ethernet Controller
12
Track ID: JATR-1076-21 Rev. 1.06
ETC [ ETC ]
