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RTL8100CL 参数 Datasheet PDF下载

RTL8100CL图片预览
型号: RTL8100CL
PDF下载: 下载PDF文件 查看货源
内容描述: 电源管理单芯片快速以太网控制器 [SINGLE-CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT]
分类和应用: 外围集成电路控制器LTE局域网以太网以太网:16GBASE-T
文件页数/大小: 73 页 / 652 K
品牌: ETC [ ETC ]
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RTL8100C & RTL8100CL  
Datasheet  
Offset  
0044h-0047h  
0048h-004Bh  
R/W  
R/W  
R/W  
Tag  
RCR  
TCTR  
Description  
Receive (Rx) Configuration Register.  
Timer CounT Register.  
This register contains a 32-bit general-purpose timer. Writing any  
value to this register will reset the original timer and start a count  
from zero.  
004Ch-004Fh  
R/W  
MPC  
Missed Packet Counter.  
Indicates the number of packets discarded due to Rx FIFO  
overflow. It is a 24-bit counter. After s/w reset, MPC is cleared.  
Only the lower 3 bytes are valid.  
When any value is written, MPC will be reset also.  
93C46 Command Register.  
Configuration Register 0.  
Configuration Register 1.  
Reserved.  
0050h  
0051h  
0052h  
0053H  
R/W  
R/W  
R/W  
-
9346CR  
CONFIG0  
CONFIG1  
-
0054h-0057h  
R /W  
TimerInt  
Timer Interrupt Register.  
Once having written a non-zero value to this register, the Timeout  
bit of the ISR register will be set whenever the TCTR reaches that  
value. The Timeout bit will never be set whilst the TimerInt register  
is zero.  
0058h  
0059h  
005Ah  
005Bh  
R/W  
R/W  
R/W  
-
MSR  
CONFIG3  
CONFIG4  
-
Media Status Register.  
Configuration register 3.  
Configuration register 4.  
Reserved.  
005Ch-005Dh  
005Eh  
005Fh  
R/W  
R
-
MULINT  
RERID  
-
Multiple Interrupt Select.  
PCI Revision ID = 10h.  
Reserved.  
0060h-0061h  
0062h-0063h  
0064h-0065h  
0066h-0067h  
0068h-0069h  
006Ah-006Bh  
006Ch-006Dh  
006Eh-006Fh  
0070h-0071h  
0072h-0073h  
0074h-0075h  
0076-0077h  
0078h-007Bh  
007Ch-007Fh  
0080h  
R
R/W  
R
R/W  
R
R
R
R
R/W  
R
R/W  
-
R/W  
R/W  
R/W  
-
R/W  
R/W  
R/W  
R/W  
R/W  
TSAD  
BMCR  
BMSR  
ANAR  
ANLPAR  
ANER  
DIS  
FCSC  
NWAYTR  
REC  
Transmit Status of All Descriptors.  
Basic Mode Control Register.  
Basic Mode Status Register.  
Auto-Negotiation Advertisement Register.  
Auto-Negotiation Link Partner Register.  
Auto-Negotiation Expansion Register.  
Disconnect Counter.  
False Carrier Sense Counter.  
N-way Test Register.  
RX_ER Counter.  
CS Configuration Register.  
CSCR  
-
Reserved.  
PHY Parameter 1.  
Twister Parameter.  
PHY Parameter 2.  
PHY1_PARM  
TW_PARM  
PHY2_PARM  
-
0081-0083h  
0084h  
0085h  
0086h  
0087h  
Reserved.  
CRC0  
CRC1  
CRC2  
CRC3  
Power Management CRC register 0 for wakeup frame 0.  
Power Management CRC register 1 for wakeup frame 1.  
Power Management CRC register 2 for wakeup frame 2.  
Power Management CRC register 3 for wakeup frame 3.  
Power Management CRC register 4 for wakeup frame 4.  
0088h  
CRC4  
Single-Chip Fast Ethernet Controller  
11  
Track ID: JATR-1076-21 Rev. 1.06