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RTL8100CL 参数 Datasheet PDF下载

RTL8100CL图片预览
型号: RTL8100CL
PDF下载: 下载PDF文件 查看货源
内容描述: 电源管理单芯片快速以太网控制器 [SINGLE-CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT]
分类和应用: 外围集成电路控制器LTE局域网以太网以太网:16GBASE-T
文件页数/大小: 73 页 / 652 K
品牌: ETC [ ETC ]
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RTL8100C & RTL8100CL  
Datasheet  
Bit  
R/W  
Symbol  
Description  
15  
R
TOK  
Transmit OK.  
Set to 1 indicates that the transmission of a packet was completed  
successfully and no transmit underrun has occurred.  
Transmit FIFO Underrun.  
14  
R
TUN  
Set to 1 if the Tx FIFO was exhausted during the transmission of a  
packet. The RTL8100C(L) can re-transfer data if the Tx FIFO  
underruns. That is, when TSD<TUN>=1, TSD<TOK>=0 and  
ISR<TOK>=1 (or ISR<TER>=1).  
13  
R/W  
R/W  
OWN  
SIZE  
OWN.  
The RTL8100C(L) sets this bit to 1 when the Tx DMA operation of  
this descriptor has completed. The driver must set this bit to 0 when  
the Transmit Byte Count (bits 0-12) is written. The default value is 1.  
Descriptor Size.  
12-0  
The total size in bytes of the data in this descriptor. If the packet  
length is more than 1792 bytes (0700h), the Tx queue will be invalid,  
i.e. the next descriptor will be written only after the OWN bit of that  
long packet’s descriptor has been set.  
5.11. ERSR: Early RX Status Register (Offset 0036h, R)  
Table 11. ERSR: Early RX Status Register  
Bit  
7-4  
3
R/W  
-
R
Symbol  
-
ERGood  
Description  
Reserved.  
Early Rx Good packet.  
This bit is set whenever a packet is completely received and the  
packet is good. Writing a 1 to this bit will clear it.  
Early Rx Bad packet.  
This bit is set whenever a packet is completely received and the  
packet is bad. Writing a 1 to this bit will clear it.  
Early Rx OverWrite.  
2
1
R
R
ERBad  
EROVW  
This bit is set when the RTL8100C(L)’s local address pointer is equal  
to CAPR. In Early Mode, this is different from buffer overflow. It  
happens when the RTL8100C(L) detects an Rx error and wants to fill  
another packet data from the beginning address of that error packet.  
Writing a 1 to this bit will clear it.  
0
R
EROK  
Early Rx OK.  
The power-on value is 0. It is set when the Rx byte count of the  
arriving packet exceeds the Rx threshold. After the whole packet is  
received, the RTL8100C(L) will set ROK or RER in ISR and clear  
this bit simultaneously. Setting this bit will invoke an ROK interrupt.  
Single-Chip Fast Ethernet Controller  
14  
Track ID: JATR-1076-21 Rev. 1.06