RTL8100C & RTL8100CL
Datasheet
Bytes
Contents
Description
19h
CONFIG4
RTL8100C(L) Configuration register 4.
Operational registers offset 5Ah.
Reserved. Do not change this field without Realtek approval.
PHY1_PARM_U PHY Parameter 1-U for RTL8100C(L).
Operational registers of the RTL8100C(L) are from 78h to 7Bh.
Reserved. Do not change this field without Realtek approval.
PHY2_PARM_U PHY Parameter 2-U for RTL8100C(L). Operational register of the RTL8100C(L) is
80h.
1Ah-1Dh
1Eh
Reserved. Do not change this field without Realtek approval.
1Fh
CONFIG_5
Do not change this field without Realtek approval.
Bit7-3: Reserved.
Bit2: Link Down Power Saving mode.
1: Disable.
0: Enable. When the cable is disconnected (Link Down), the analog part will power
itself down (PHY Tx part and Twister) automatically except for the PHY Rx part and
part of the twister that monitors the SD signal in case the cable is reconnected and the
Link is established again.
Bit1: LANWake signal Enable/Disable.
1: Enable LANWake signal
0: Disable LANWake signal
Bit0: PME_Status bit property.
1: The PME_Status bit can be reset by PCI reset or by software if
D3cold_support_PME is 0. If D3cold_support_PME=1, the PME_Status bit is a
sticky bit
0: The PME_Status bit is always a sticky bit and can only be reset by software
Reserved. Do not change this field without Realtek approval.
Twister Parameter U for the RTL8100C(L).
Operational registers of the RTL8100C(L) are 7Ch-7Fh.
Reserved. Do not change this field without Realtek approval.
Twister Parameter T for the RTL8100C(L).
20h-23h
24h-27h
28h-2Bh
2Ch
TW_PARM_U
TW_PARM_T
Operational registers of the RTL8100C(L) are 7Ch-7Fh.
PHY1_PARM_T Reserved. Do not change this field without Realtek approval.
PHY Parameter 1-T for the RTL8100C(L).
Operational registers of the RTL8100C(L) are from 78h to 7Bh.
PHY2_PARM_T Reserved. Do not change this field without Realtek approval.
PHY Parameter 2-T for the RTL8100C(L).
Operational register of the RTL8100C(L) is 80h.
2Dh-31h
32h-33h
-
Reserved.
CheckSum
Reserved. Do not change this field without Realtek approval.
Checksum of the EEPROM content.
34h-3Eh
3Fh
-
Reserved. Do not change this field without Realtek approval.
Reserved. Do not change this field without Realtek approval.
PXE ROM code parameter.
PXE_Para
40h-7Fh
VPD_Data
VPD data field. Offset 40h is the start address of the VPD data.
Single-Chip Fast Ethernet Controller
36
Track ID: JATR-1076-21 Rev. 1.06
ETC [ ETC ]
