PRELIMINARY
PCT1789W DATA SHEET
PCT789T-A PCI CONFIGURATION REGISTERS
!!
PCI Configuration Register Detailed Description
Configuration ID
(00h, R)
DID[15:0]
31
15
30
29
13
28
12
27
11
26
10
25
9
24
23
22
6
21
5
20
4
19
3
18
2
17
1
16
VID[15:0]
14
8
7
0
Bit Definitions:
Bits
31:16
Name
Description
DID[15:0]
Device ID (R: default 789xh). Unique PCT789T-A ID number. The last three bits
of the ID are loaded into this register through three strapped input pins, IDID[2:0],
during the power-on reset period.
15:0
VID[15:0]
Vendor ID (R: default 134Dh). Specifies the manufacturer of the PCT789T-A:
PC-TEL Inc.
Command and Status Configuration
(04h, R/W)
PERR SSERR
0
0
0
DEVSEL[1:0]
0
0
0
0
CAP
0
0
0
0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
SERREN
1
RSPPE
0
0
0
0
0
IOACS
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit Definitions:
Bits
Name
PERR
Description
31
30
Detected parity error (R/W: default 0b). Set when the PCT789T-A detects a par-
ity error.
SSERR
Signaled system error (R/W: default 0b). Set when the PCT789T-A asserts
SERR#.
29:27
26:25
Reserved
Reserved. Read returns zero.
DEVSEL[1:0]
DEVSEL timing (R: default 01b). Indicates the timing of the assertion of the
DEVSEL* pin. The PCT789T-A is set for median speed PCI device.
24:21
20
Reserved
CAP
Reserved. Read returns zero.
Capabilities (R: default 1b). When set, indicates that the PCT789T-A is capable
of handling PCI power management.
19:9
8
Reserved
SERREN
Reserved. Read returns zero.
System error enable (R/W: default 0b). When set, enables the SERR# driver on
the PCT789T-A to report a system error.
7
6
Reserved
RSPPE
Reserved. Read returns one.
Parity error response (R/W: default 0b). When set, signals the PCT789T-A to
assert PERR* after a parity error detection. Otherwise, any parity error detection
is ignored. Parity checking is disabled after reset.
5:1
0
Reserved
IOACS
Reserved. Read returns zero.
I/O space access (W). Set to allow the PCT789T-A to respond to I/O space
accesses.
PRELIMINARY
PC-TEL, Inc.
30
1789W0DOCDAT06A-0299
ETC [ ETC ]
