2.5 FIFO Clock Conversion
The L64777 uses a dual-ported RAM to implement the circular buffer
FIFO function. The circular buffer has a write pointer driven by ICLK and
a read pointer driven by the Symbol clock, OCLK/4. The device does not
prevent collisions of the pointers; rather, the PLL-VCO follow-up time and
proper initial setup of the pointer distance must guarantee this.
For FIFO initialization, the L64777 loads a user-programmable pointer
distance of 0 to 127 cycles (the FIFO delay value of Register 2 in
Group 2) into the read address pointer (after each microprocessor delay
register access) and sets the write address pointer to zero (see
Figure 2.9). After this initialization, both pointers run free, and the OCLK
to ICLK frequency relationship determines how the read and write
pointers advance.
To allow outside watching of the asynchronous pointers, an alarm
comparator indicates when both pointers are equal. Because both
counters are Gray Code counters (in which changes occur only in one
bit) the spikes and glitches of the asynchronous signals are minimized.
When specifying the microprocessor download value for the read pointer
initialization, you must use Gray Code. The write pointer also is Gray
Code counter-driven; it initializes to zero when the read counter is
loaded.
Figure 2.9 FIFO Pointer Concept
Circular
Buffer
Read Pointer
Zero
128 Words
Properly programmed delay values in Gray Code guarantee that the read
pointer is directly opposite the write pointer most of the time; this
increases system immunity against PLL frequency swings, which might
occur during the phases of an unstable input signal. Smaller distances
also can reduce system delay.
2-16
Modulator Architecture
ETC [ ETC ]
