Register Description
3.4.19
PMBASE—Prefetchable Memory Base Address Register
(Device 1)
Address Offset:
Default Value:
Access:
24–25h
FFF0h
Read/Write
16 bits
Size:
This register controls the CPU to AGP prefetchable memory accesses routing based on the
following formula:
PREFETCHABLE_MEMORY_BASE=< address =<PREFETCHABLE_MEMORY_LIMIT
This register must be initialized by the configuration software.
Bit
Description
Prefetchable Memory Address Base(PMEM_BASE).Corresponds to A[31:20] of the memory
address.
15: 4
3:0
Default=FFF0h
Reserved.
3.4.20
PMLIMIT—Prefetchable Memory Limit Address Register
(Device 1)
Address Offset:
Default Value:
Access:
26–27h
0000h
Read/Write
16 bits
Size:
This register controls the CPU to AGP prefetchable memory accesses routing based on the
following formula:
PREFETCHABLE_MEMORY_BASE=< address =<PREFETCHABLE_MEMORY_LIMIT
This register must be initialized by the configuration software.
Note: The prefetchable memory range is supported to allow segregation by the configuration software
between the memory ranges that must be defined as Uncachable and the ones that can be
designated as a USWC (i.e. prefetchable) from the CPU perspective.
Bit
Description
Prefetchable Memory Address Limit (PMEM_LIMIT). Corresponds to A[31:20] of the memory
address. Default=0
15: 4
3:0
Reserved.
3-58
82443BX Host Bridge Datasheet
ETC [ ETC ]
