Register Description
3.4.12
SUBUSN—Subordinate Bus Number Register (Device 1)
Offset:
Default:
Access:
Size:
1Ah
00h
Read /Write
8 bits
This register identifies the subordinate bus (if any) that resides at the level below AGP.This number
is programmed by the PCI configuration software to allow mapping of configuration cycles to AGP.
Bit
Descriptions
7:0
Bus Number. Programmable.
3.4.13
SMLT—Secondary Master Latency Timer Register
(Device 1)
Address Offset:
Default Value:
Access:
1Bh
00h
Read/Write
8 bits
Size:
This register control the bus tenure of the 82443BX on AGP the same way the Device 0 MLT
controls the access to the PCI bus.
Bit
Description
7:3
2:0
Secondary MLT Counter Value. The default is 0s (i.e,. SMLT disabled)
Reserved.
3.4.14
IOBASE—I/O Base Address Register (Device 1)
Address Offset:
Default Value:
Access:
1Ch
F0h
Read/Write
8 bits
Size:
This register control the CPU to AGP I/O access routing based on the following formula:
IO_BASE=< address =<IO_LIMIT
Bit
Description
7:4
3:0
I/O Address Base. Corresponds to A[15:12] of the I/O address. Default = Fh
Reserved.
3-54
82443BX Host Bridge Datasheet
ETC [ ETC ]
