Register Description
3.3.27
SCRR—Suspend CBR Refresh Rate Register (Device 0)
Address Offset:
Default Value:
Access
7Bh–7Ch
0038h
Read/Write
16 Bits
Size
Bit
Description
15:13
Reserved.
Suspend CBR refresh Rate Auto Adjust Enable (SRRAEN). SRRAEN bit is cleared to its default
during cold reset only. It is not affected by PCIRST# during resume from suspend.
0 = Disable (default). Indicates that the suspend CBR refresh rate is not updated by the 82443BX
hardware to track the system operating conditions. In this case, it is expected that BIOS will set
the SRR to reflect the worst case operating conditions so that minimum refresh rate will be
provided.
12
1 = Enable. Indicates that the 82443BX hardware adjusts the suspend refresh rate according to
system operating conditions by comparing the number of OSCCLKs in a given time. This mode
allows the system to dynamically adjust the refresh rate and thus minimize suspend power
consumption while guaranteeing required refresh rate.
Suspend CBR Refresh Rate (SRR). The rate is loaded into the counter which counts down on
OSCCLK rising edges. When it expires, a suspend CBR refresh request is triggered. This bit field
may be loaded by BIOS to reflect the desirable refresh rate. In addition, the 82443BX will update it
automatically, when the above SRRAEN = 1. In either case, the register is accessible for read and
write operation at all times.
•
•
•
This 12-bit field provides a dynamic range greater than the maximum CBR refresh rate that is
supported of 249.6uSEC.
11:0
SRR bit field is cleared to its default during cold reset only. It is not affected by PCIRST# during
resume from suspend.
The default value of this register is 038h, or 56 decimal. It represents a 15.5uS time between
refreshes with the slowest corner OSCCLK cycle time of 270nS.
3-34
82443BX Host Bridge Datasheet
ETC [ ETC ]
