Register Description
3.3.23
RPS—SDRAM Row Page Size Register (Device 0)
Address Offset:
Default Value:
Access:
74h–75h
0000h
Read/Write
16 bits
Size:
This register sets the row page size for SDRAM only. For EDO memory, the page size is fixed at
2 KB.
Bit
Description
Page Size (PS). Each pair of bits in this register indicate the page size used for one row of DRAM.
The encoding of the two bit fields.
Bits[1:0]
Page Size
00
01
10
11
2 KB
4 KB
8 KB
Reserved
RPS bits
Corresponding DRB register
15:0
1:0
3:2
5:4
7:6
DRB[0], row 0
DRB[1], row 1
DRB[2], row 2
DRB[3], row 3
DRB[4], row 4
DRB[5], row 5
DRB[6], row 6
DRB[7], row 7
9:8
11:10
13:12
15:14
3.3.24
SDRAMC—SDRAM Control Register (Device 0)
Address Offset:
Default Value:
Access:
76h–77h
00h
Read/Write
Size:
16 bits
Bit
Description
15:10
9:8
Reserved
Idle/Pipeline DRAM Leadoff Timing (IPDLT). Adds a clock delay to the lead-off clock count
when bits 9:8 are set to 01. All other settings are illegal.
3-30
82443BX Host Bridge Datasheet
ETC [ ETC ]
