Register Description
3.3.26
PMCR—Power Management Control Register (Device 0)
Address Offset:
Default Value:
Access
7Ah
0000_S0S0b
Read/Write
8 Bits
Size
Bit
Description
Power Down SDRAM Enable (PDSE).
1 = Enable. When PDSE=1, an SDRAM row in idle state will be issued a power down
command. The SDRAM row will exit power down mode only when there is a request to
access this particular row.
7
6
0 = Disable
ACPI Control Register Enable (SCRE).
1 = Enable. The ACPI control register in the 82443BX is enabled, and all CPU cycles to IO
address 0022h are handled by the 82443BX and are not forwarded to PCI.
0 = Disable (default). All CPU cycles to IO address 0022h are passed on to the PCI bus.
Suspend Refresh Type (SRT). This bit determines what type of EDO DRAM refresh is used
during Power On Suspend (POS/STR) or Suspend to RAM modes. SRT has no effect on
SDRAM refresh.
5
1 = Self refresh mode
0 = CBR fresh mode
NOTE: When PCIRST# assertion occurs during POS/STR, this bit is not reset to ‘0’.
Normal Refresh Enable (NREF_EN). This bit is used to enable normal refresh operation
following a POS/STR state. After coming out of reset the software must set this bit before
doing an access to memory.
4
3
2
1 = Enable
0 = Disable
Quick Start Mode (QSTART) (RO).
1 = Quick start mode of operation is enabled for the processor. This mode is entered using a
strapping option that is sampled by the 82443BX and the CPU during reset. This register
bit is Read Only and a configuration write to it is ignored.
Gated Clock Enable (GCLKEN). GCLKEN enables internal dynamic clock gating in the
82443BX when a AGPset “IDLE” state occurs. This happens when the 82443BX detects an
idle state on all its buses.
1 = Enable
0 = Disable
AGP Disable (AGP_DIS). This register bit is Read Only and a configuration write to it is
ignored.
1 = Disable. The AGP interface and the clocks of AGP associated logic are permanently
disabled. This mode is entered using a strapping option that is sampled by the 82443BX
during reset.
1
0
0 = Enable
CPU reset without PCIRST enable (CRst_En). This bit enables the 82443BX to assert CPU
reset without an incoming PCIRST#. This option allows the reset of the processor when the
system is coming out of POS state. Defaults to ‘0’ upon PCIRST# assertion.
1 = Enable
0 = Disable
NOTE: When PCIRST# assertion occurs during POS/STR, this bit is not reset to ‘0’.
82443BX Host Bridge Datasheet
3-33
ETC [ ETC ]
