Register Description
3.3.4
PCISTS—PCI Status Register (Device 0)
Address Offset:
Default Value:
Access:
06–07h
0210h/0200h
Read Only, Read/Write Clear
16 bits
Size:
PCISTS is a 16-bit status register that reports the occurrence of a PCI master abort and PCI target
abort on the PCI bus. PCISTS also indicates the DEVSEL# timing that has been set by the
82443BX hardware for target responses on the PCI bus. Bits [15:12] and bit 8 are read/write clear
and bits [10:9] are read only.
Bit
Descriptions
Detected Parity Error (DPE). Note that the function of this bit is not affected by the PERRE bit.
PERR# is not implemented in the 82443BX.
15
1 = Indicates 82443BX’s detection of a parity error in the address or data phase of PCI bus
transactions.
0 = Software sets DPE to 0 by writing a 1 to this bit.
Signaled System Error (SSE).
1 = This bit is set to 1 when the 82443BX asserts SERR# for any enabled error condition under
device 0.
14
13
12
0 = Software sets SSE to 0 by writing a 1 to this bit.
Received Master Abort Status (RMAS). Note that Master abort is the normal and expected
termination of PCI special cycles.
1 = When the 82443BX terminates a PCI bus transaction (82443BX is a PCI master) with an
unexpected master abort, this bit is set to 1.
0 = Software resets this bit to 0 by writing a 1 to it.
Received Target Abort Status (RTAS).
1 = When a 82443BX-initiated PCI transaction is terminated with a target abort, RTAS is set to 1.
The 82443BX also asserts SERR# if enabled in the ERRCMD register.
0 = Software resets RTAS to 0 by writing a 1 to it.
Signaled Target Abort Status (STAS). The 82443BX does not generate target abort.
11
0 = Hardwired to a 0
DEVSEL# Timing (DEVT). This 2-bit field indicates the timing of the DEVSEL# signal when the
82443BX responds as a target on PCI, and indicates the time when a valid DEVSEL# can be
sampled by the initiator of the PCI cycle.
10:9
01 = Medium (hardwired to 01)
Data Parity Detected (DPD). 82443BX does not implement the PERR# pin. However, data parity
errors are still detected and reported on SERR# (if enabled by SERRE and PERRE).
8
0 = Hardwired to 0
Fast Back-to-Back (FB2B). The 82443BX as a target does not support fast back-to-back
transactions on the PCI bus.
7
0 = Hardwired to 0
Reserved.
6:5
Capability List (CLIST).
4
1 = When the AGP DIS bit (PMCR[1]) is set to 0, this bit is set to 1.
0 = When the AGP DIS bit (PMCR[1]) is set to 1, this bit is set 0.
3:0
Reserved.
3-12
82443BX Host Bridge Datasheet
ETC [ ETC ]
