Register Description
3.3.8
MLT—Master Latency Timer Register (Device 0)
Address Offset:
Default Value:
Access:
0Dh
00h
Read/Write
8 bits
Size:
This register controls the amount of time that 82443BX can burst data on the PCI Bus as a PCI
master. The MLT[2:0] bits are reserved and assumed to be 0 when determining the Count Value.
Bit
Description
Master Latency Timer Count Value for PCI Bus Access. MLT is an 8-bit register that controls
the amount of time the 82443BX, as a PCI bus master, can burst data on the PCI Bus. The
default value of MLT is 00h and disables this function. For example, if the MLT is programmed to
18h, then the value is 24 PCI clocks.
7:3
2:0
Reserved.
3.3.9
HDR—Header Type Register (Device 0)
Offset:
Default:
Access:
Size:
0Eh
00h
Read Only
8 bits
This register identifies the header layout of the configuration space.
Bit
Descriptions
Header Type (HEADT). This read only field always returns 0 when read. Writes have no affect
on this field.
7:0
3.3.10
APBASE—Aperture Base Configuration Register (Device 0)
Offset:
Default:
Access:
Size:
10–13h
00000008h
Read/Write, Read Only
32 bits
The APBASE is a normal PCI Base Address register that is used to request the base of the Graphics
Aperture. The normal PCI Configuration mechanism defines the base address configuration
register such that only a fixed amount of space can be requested (dependent on which bits are
hardwired to “0” or behave as hardwired to “0”). To allow for flexibility (of the aperture) an
additional register called APSIZE is used as a “back-end” register to control which bits of the
APBASE will behave as hardwired to “0”. This register will be programmed by the 82443BX
specific BIOS code that will run before any of the generic configuration software is run.
Note: Bit 9 of the NBXCFG register is used to prevent accesses to the aperture range before this register
is initialized by the configuration software and appropriate translation table structure has been
established in the main memory.
3-14
82443BX Host Bridge Datasheet
ETC [ ETC ]
