TrueSpeech® Co-Processor
PRELIMINARY/CONFIDENTIAL
Version: 1.18
Burst Mode
DREQ
DACK/
HSTRD/
HSTWR/
TX
Ready
or
RX
Ready
Figure 4-5:
Burst Mode DMA
In Burst Mode, DREQ remains asserted until the RX or TX Ready bit is cleared by the final counter increment. Byte
transfers are clocked by the HSTRD/ or HSTWR/ signals as appropriate. The positive going edge of these signals
toggles the DMA byte select. The data buffer address counter increments on alternate cycles, i.e. each time a high
byte is accessed. When the counter reaches the Frame Size limit the RX or TX Ready and DREQ signals are
cleared.
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DSP GROUP, INC., 3120 SCOTT BOULEVARD CT8022A11AQC FW Revision 0118
SANTA CLARA, CA 95054 PH: 408 986 – 4300 FAX: 408 986 – 4490
All specifications are subject to change without prior notice.
ETC [ ETC ]
