Version: 1.18
PRELIMINARY/CONFIDENTIAL
TrueSpeech® Co-Processor
5.1.1
Master/Slave
The CT8022 can be operated in CODEC master or slave mode.
In master mode, the SCLK and FSYNC signal pins are outputs. The clock frequencies for the two signals are
generated by programmable integer division from the internal CT8022 DSP core clock. To achieve an SCLK
frequency of 2.048 MHz for operation with an A-law or µ-law CODEC, the CT8022 internal clock should be 45.056
MHz (4.096 MHz crystal). 45.056 MHz = 22 * 2.048 MHz.
In slave mode, the SCLK and FSYNC signals pins are inputs. The SCLK and FSYNC signals must be generated
externally. For TrueSpeech G.723.1 operation, the FSYNC frequency should be exactly 8.0 KHz. In slave mode, it
is possible to connect the CT8022 CODEC interface to a TDM (Time Division Multiplexed) bus.
For support of G.722 7 KHz wideband ADPCM (only), the CT8022 must be operated with an external CODEC that
supports operation at 16K samples/sec.
Following reset, the CT8022 CODEC interface will be in slave mode, so that SCLK and FSYNC are inputs.
5.1.2
8-bit A-law/µ-law and 16-bit Linear CODEC
The CT8022 CODEC interface can be programmed by the Host to operate in 8-bit or 16-bit mode. In 8-bit mode for
each FSYNC, 8 data bits are shifted out of the DX0 and DX1 pins, and 8 data bits are shifted in at the DR0 and DR1
pins. In 16-bit mode for each FSYNC, 16 data bits are shifted out of the DX0 and DX1 pins, and 16 data bits are
shifted in at the DR0 and DR1 pins.
In 8-bit mode, the data format may be either µ-law or A-law.
In 16-bit mode, the data format is 16-bit linear, with the most significant bit shift in/out first.
5.1.3
Short or Long FSYNC
In master mode, the CT8022 may be operated in short or long FSYNC mode. In short FSYNC mode, the FSYNC
pulse is 1 SCLK period wide. The timing of the FSYNC pulse relative to the data bits conforms to the telecom
industry standard for short FSYNC for PCM A-law/µ-law codes when SCLK = 2.048 MHz, and FSYNC =
8.00 KHz. In long FSYNC mode, the FSYNC pulse is 8 or 16 SCLK periods wide, depending on the data width
selected. In this mode, the FSYNC pulse is aligned with the receive and transmit time slot of the data bits.
In slave mode, the width of the FSYNC pulse is not important. Selecting long or short FSYNC mode only affects the
assumed timing position of the FSYNC relative to the data bits.
5.1.4
Programmable SCLK and FSYNC Rates
In master mode, the SCLK and FSYNC rates are fully programmable by the Host. This enables Host selection of the
CODEC sample rate based on simple integer division from the internal CT8022 clock.
SCLK is generated by a division-by-(N+1) from the internal CT8022 clock. The divisor may be in the range
of 4 <= (N+1) <= 32. If the internal CT8022 clock is 45.056, then setting N = 21 will produce a 2.048 MHz SCLK.
FSYNC is generated by a division -by -(M+1) from SCLK. The divisor may be in the range of 18 <= M <= 1023. If
SCLK = 2.048 MHz and M = 255, then FSYNC will be 8.0 KHz.
CT8022A11AQC FW Revision 0118 DSP GROUP, INC., 3120 SCOTT BOULEVARD
SANTA CLARA, CA 95054 PH: 408 986 – 4300 FAX: 408 986 – 4490
41
All specifications are subject to change without prior notice.
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