TrueSpeech® Co-Processor
PRELIMINARY/CONFIDENTIAL
Version: 1.18
The following table shows possible clock frequencies:
MAINCLOCK = 45.056 MHz (4.096 MHz crystal)
SCLK
FSYNC
N
M
2.048 MHz
2.048 MHz
2.816 MHz
8.000 KHz
11.011 KHz
11.043 KHz
21
21
15
255
185
254
Note that the AT&T T7525 16-bit linear CODEC requires that the SCLK frequency be exactly 256 times the
FSYNC frequency. When using this CODEC, SCLK must be 2.048 MHz in order to achieve a FSYNC frequency of
8.000 KHz.
For supported SCLK-to-FSYNC ratios, please consult the external CODEC manufacturer’s data sheet. Note that
some G.711 A-law/µ-law CODECs provide strapping options which access different available ranges for the
SCLK-to-FSYNC ratio (e.g. for operation at E1 2.048 MHz 32 channel rate or T1 1.544 MHz 24 channel rate). In
general, the choice of SCLK frequency often controls the effective audio bandwidth of the CODEC’s anti-aliasing
filter.
For an 8-bit CODEC, the CT8022 requires that the SCLK frequency is at least 16 times the FSYNC frequency.
For a 16-bit CODEC, the CT8022 requires that the SCLK frequency is at least 32 times the FSYNC frequency.
The CT8022 may be operated at a lower core clock rate to reduce the power consumption of the device, if the clock
rate chosen provides sufficient MIP s for the modes of operation used. Operating the CT8022 at a lower clock rate
requires that the Host change the SCLK and FSYNC division factors to obtain the desired A-to-D sample rate.
5.1.5
Stop CODEC
In Master mode, the Stop CODEC command can be used to halt operation of the CODEC interface. In this state, the
FSYNC and SCLK signals are held low. Stop CODEC in Slave mode has no effect.
42
DSP GROUP, INC., 3120 SCOTT BOULEVARD CT8022A11AQC FW Revision 0118
SANTA CLARA, CA 95054 PH: 408 986 – 4300 FAX: 408 986 – 4490
All specifications are subject to change without prior notice.
ETC [ ETC ]
