Version: 1.18
PRELIMINARY/CONFIDENTIAL
TrueSpeech® Co-Processor
9.24.6
Inter-Frame Idle Power Save
When the CT8022 is operating in Host-CODEC mode and providing real-time speech input/output during
playback/record operation, the CT8022 executes an internal idle loop while waiting to begin processing of the next
speech frame.
During this Inter-Frame Idle period, the CT8022 can be programmed to dynamically reduce the internal DSP core
clock rate in order to further conserve power.
The command to set the Inter-Frame Idle Clock Division Factor is:
C1:
S1:
C2:
S2:
514AH
514AH
000XH
000XH
where X+1 is the division factor.
Note: The Inter-Frame Idle Clock Division Factor is reset each time the primary clock division factor is set
using the 0FEXH command. Each time the Primary Clock Division Factor is programmed, the Inter-
Frame Idle Clock Division Factor is set to the same value as the Primary Clock Division Factor.
Care should be taken not to reduce the clock to too low a value during the Inter-Frame Idle period as this may cause
the CT8022 to respond as if there are insufficient MIPS available for overall processing. This may result in the AEC
convergence/training being limited. Refer to Section 9.15.3.1.
CT8022A11AQC FW Revision 0118 DSP GROUP, INC., 3120 SCOTT BOULEVARD
SANTA CLARA, CA 95054 PH: 408 986 – 4300 FAX: 408 986 – 4490
157
All specifications are subject to change without prior notice.
ETC [ ETC ]
