R
XC5200 Series Field Programmable Gate Arrays
TO DIN OF OPTIONAL
DAISY-CHAINED FPGAS
HIGH
or
3.3 K
N/C
M2
LOW
N/C
M0 M1
TO CCLK OF OPTIONAL
DAISY-CHAINED FPGAS
CCLK
DOUT
NOTE:M0 can be shorted
to Ground if not used
as I/O.
M0 M1 M2
. . .
. . .
. . .
. . .
. . .
A17
A16
A15
A14
A13
A12
A11
A10
A9
XC5200
Master
Parallel
DIN
DOUT
VCC
EPROM
(8K x 8)
(OR LARGER)
CCLK
4.7K
XC5200/
XC4000E/EX/
Spartan
USER CONTROL OF HIGHER
ORDER PROM ADDRESS BITS
CAN BE USED TO SELECT BETWEEN
ALTERNATIVE CONFIGURATIONS
INIT
A12
A11
A10
A9
SLAVE
PROGRAM
PROGRAM
DONE
INIT
D7
D6
D5
D4
D3
D2
D1
D0
A8
A8
A7
A7
D7
D6
D5
D4
D3
D2
D1
D0
A6
A6
A5
A5
A4
A4
A3
A3
A2
A2
A1
A1
A0
A0
DONE
OE
CE
DATA BUS
8
PROGRAM
X9004_01
Figure 31: Master Parallel Mode Circuit Diagram
7-116
November 5, 1998 (Version 5.2)
ETC [ ETC ]
