R
XC5200 Series Field Programmable Gate Arrays
DONE High to active user I/O is controlled by an option to
the bitstream generation software.
Q3
Q2
Q1/Q4
DONE
IN
STARTUP
IOBs OPERATIONAL PER CONFIGURATION
*
*
GLOBAL RESET OF
ALL CLB FLIP-FLOPS/LATCHES
1
0
GR ENABLE
GR INVERT
STARTUP.GR
CONTROLLED BY STARTUP SYMBOL
IN THE USER SCHEMATIC (SEE
LIBRARIES GUIDE)
STARTUP.GTS
GTS INVERT
GTS ENABLE
0
1
GLOBAL 3-STATE OF ALL IOBs
Q
S
R
DONE
" FINISHED "
ENABLES BOUNDARY
SCAN, READBACK AND
CONTROLS THE OSCILLATOR
*
1
0
1
0
Q0
Q1
Q2
Q3
Q4
1
FULL
LENGTH COUNT
S
Q
D
Q
D
Q
D
Q
D
Q
0
M
K
K
K
K
K
*
CLEAR MEMORY
CCLK
0
1
STARTUP.CLK
USER NET
M
CONFIGURATION BIT OPTIONS SELECTED BY USER
X9002
*
*
Figure 26: Start-up Logic
Release of Global Reset After DONE Goes High
Configuration Through the Boundary Scan
Pins
By default, Global Reset (GR) is released two CCLK cycles
after the DONE pin goes High. If CCLK is not clocked twice
after DONE goes High, all flip-flops are held in their initial
reset state. The delay from DONE High to GR inactive is
controlled by an option to the bitstream generation soft-
ware.
XC5200-Series devices can be configured through the
boundary scan pins.
For detailed information, refer to the Xilinx application note
XAPP017, “Boundary Scan in XC4000 and XC5200
Devices.”
Configuration Complete After DONE Goes High
Readback
Three full CCLK cycles are required after the DONE pin
goes High, as shown in Figure 25 on page 109. If CCLK is
not clocked three times after DONE goes High, readback
cannot be initiated and most boundary scan instructions
cannot be used.
The user can read back the content of configuration mem-
ory and the level of certain internal nodes without interfer-
ing with the normal operation of the device.
Readback not only reports the downloaded configuration
bits, but can also include the present state of the device,
represented by the content of all flip-flops and latches in
CLBs.
7-112
November 5, 1998 (Version 5.2)
ETC [ ETC ]
