R
XC5200 Series Field Programmable Gate Arrays
Initialization
X2
X15
This phase clears the configuration memory and estab-
lishes the configuration mode.
X16
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
15
The configuration memory is cleared at the rate of one
frame per internal clock cycle (nominally 1 MHz). An
open-drain bidirectional signal, INIT, is released when the
configuration memory is completely cleared. The device
then tests for the absence of an external active-low level on
INIT. The mode lines are sampled two internal clock cycles
later (nominally 2 µs).
SERIAL DATA IN
Polynomial: X16 + X15 + X2 + 1
1
1
1
1
1
0
15 14 13 12 11 10
9
8
7
6
5
LAST DATA FRAME
CRC – CHECKSUM
X1789
Readback Data Stream
The master device waits an additional 32 µs to 256 µs
(nominally 64-128 µs) to provide adequate time for all of the
slave devices to recognize the release of INIT as well. Then
the master device enters the Configuration phase.
Figure 23: Circuit for Generating CRC-16
Configuration Sequence
There are four major steps in the XC5200-Series power-up
configuration sequence.
V
No
Boundary Scan
Instructions
Available:
CC
3V
•
•
•
•
Power-On Time-Out
Initialization
Configuration
Start-Up
Yes
Generate
One Time-Out Pulse
of 4 ms
PROGRAM
= Low
Yes
EXTEST*
SAMPLE/PRELOAD*
BYPASS
The full process is illustrated in Figure 24.
Completely Clear
Configuration
Memory
~1.3 µs per Frame
CONFIGURE*
Power-On Time-Out
(*only when PROGRAM = High)
INIT
High? if
Master
No
An internal power-on reset circuit is triggered when power
is applied. When VCC reaches the voltage at which portions
Yes
of the FPGA begin to operate (i.e., performs
a
Sample
write-and-read test of a sample pair of configuration mem-
ory bits), the programmable I/O buffers are 3-stated with
active high-impedance pull-up resistors. A time-out delay
— nominally 4 ms — is initiated to allow the power-supply
voltage to stabilize. For correct operation the power supply
must reach VCC(min) by the end of the time-out, and must
not dip below it thereafter.
Mode Lines
Master CCLK
Goes Active after
50 to 250 µs
Load One
Configuration
Data Frame
Yes
Frame
Error
Pull INIT Low
and Stop
No
There is no distinction between master and slave modes
with regard to the time-out delay. Instead, the INIT line is
used to ensure that all daisy-chained devices have com-
pleted initialization. Since XC2000 devices do not have this
signal, extra care must be taken to guarantee proper oper-
ation when daisy-chaining them with XC5200 devices. For
proper operation with XC3000 devices, the RESET signal,
which is used in XC3000 to delay configuration, should be
connected to INIT.
SAMPLE/PRELOAD
BYPASS
Config-
uration
memory
Full
No
Yes
Pass
Configuration
Data to DOUT
CCLK
Count Equals
Length
No
Count
Yes
Start-Up
Sequence
If the time-out delay is insufficient, configuration should be
delayed by holding the INIT pin Low until the power supply
has reached operating levels.
F
Operational
EXTEST
SAMPLE PRELOAD
BYPASS
If Boundary Scan
is Selected
USER 1
USER 2
CONFIGURE
READBACK
This delay is applied only on power-up. It is not applied
when reconfiguring an FPGA by pulsing the PROGRAM
pin Low. During all three phases — Power-on, Initialization,
and Configuration — DONE is held Low; HDC, LDC, and
INIT are active; DOUT is driven; and all I/O buffers are dis-
abled.
X9017
Figure 24: Configuration Sequence
7-108
November 5, 1998 (Version 5.2)
ETC [ ETC ]
