R
XC5200 Series Field Programmable Gate Arrays
When the UCLK_SYNC option is enabled, the user can
externally hold the open-drain DONE output Low, and thus
stall all further progress in the start-up sequence until
DONE is released and has gone High. This option can be
used to force synchronization of several FPGAs to a com-
mon user clock, or to guarantee that all devices are suc-
cessfully configured before any I/Os go active.
ship between CCLK and the user clock. This arbitration
causes an unavoidable one-cycle uncertainty in the timing
of the rest of the start-up sequence.
DONE Goes High to Signal End of Configuration
In all configuration modes except Express mode,
XC5200-Series devices read the expected length count
from the bitstream and store it in an internal register. The
length count varies according to the number of devices and
the composition of the daisy chain. Each device also
counts the number of CCLKs during configuration.
If either of these two options is selected, and no user clock
is specified in the design or attached to the device, the chip
could reach a point where the configuration of the device is
complete and the Done pin is asserted, but the outputs do
not become active. The solution is either to recreate the
bitstream specifying the start-up clock as CCLK, or to sup-
ply the appropriate user clock.
Two conditions have to be met in order for the DONE pin to
go high:
•
•
the chip's internal memory must be full, and
the configuration length count must be met, exactly.
Start-up Sequence
This is important because the counter that determines
when the length count is met begins with the very first
CCLK, not the first one after the preamble.
The Start-up sequence begins when the configuration
memory is full, and the total number of configuration clocks
received since INIT went High equals the loaded value of
the length count.
Therefore, if a stray bit is inserted before the preamble, or
the data source is not ready at the time of the first CCLK,
the internal counter that holds the number of CCLKs will be
one ahead of the actual number of data bits read. At the
end of configuration, the configuration memory will be full,
but the number of bits in the internal counter will not match
the expected length count.
The next rising clock edge sets a flip-flop Q0, shown in
Figure 26. Q0 is the leading bit of a 5-bit shift register. The
outputs of this register can be programmed to control three
events.
•
•
The release of the open-drain DONE output
The change of configuration-related pins to the user
function, activating all IOBs.
7
As a consequence, a Master mode device will continue to
send out CCLKs until the internal counter turns over to
•
The termination of the global Set/Reset initialization of
all CLB and IOB storage elements.
zero, and then reaches the correct length count a second
24
time. This will take several seconds [2
CCLK period]
The DONE pin can also be wire-ANDed with DONE pins of
other FPGAs or with other external signals, and can then
be used as input to bit Q3 of the start-up register. This is
called “Start-up Timing Synchronous to Done In” and is
selected by either CCLK_SYNC or UCLK_SYNC.
— which is sometimes interpreted as the device not config-
uring at all.
If it is not possible to have the data ready at the time of the
first CCLK, the problem can be avoided by increasing the
number in the length count by the appropriate value.
When DONE is not used as an input, the operation is called
“Start-up Timing Not Synchronous to DONE In,” and is
selected by either CCLK_NOSYNC or UCLK_NOSYNC.
In Express mode, there is no length count. The DONE pin
for each device goes High when the device has received its
quota of configuration data. Wiring the DONE pins of sev-
eral devices together delays start-up of all devices until all
are fully configured.
As a configuration option, the start-up control register
beyond Q0 can be clocked either by subsequent CCLK
pulses or from an on-chip user net called STARTUP.CLK.
These signals can be accessed by placing the STARTUP
library symbol.
Note that DONE is an open-drain output and does not go
High unless an internal pull-up is activated or an external
pull-up is attached. The internal pull-up is activated as the
default by the bitstream generation software.
Start-up from CCLK
If CCLK is used to drive the start-up, Q0 through Q3 pro-
vide the timing. Heavy lines in Figure 25 show the default
timing, which is compatible with XC2000 and XC3000
devices using early DONE and late Reset. The thin lines
indicate all other possible timing options.
Release of User I/O After DONE Goes High
By default, the user I/O are released one CCLK cycle after
the DONE pin goes High. If CCLK is not clocked after
DONE goes High, the outputs remain in their initial state —
3-stated, with a 20 kΩ - 100 kΩ pull-up. The delay from
Start-up from a User Clock (STARTUP.CLK)
When, instead of CCLK, a user-supplied start-up clock is
selected, Q1 is used to bridge the unknown phase relation-
November 5, 1998 (Version 5.2)
7-111
ETC [ ETC ]
