R
XC5200 Series Field Programmable Gate Arrays
Length Count Match
CCLK Period
CCLK
F
DONE
I/O
XC2000
Global Reset
F = Finished, no more
configuration clocks needed
F
DONE
I/O
Daisy-chain lead device
must have latest F
XC3000
Heavy lines describe
default timing
Global Reset
F
DONE
I/O
C1
C2
C2
C3
C3
C4
C4
XC4000E/EX
XC5200/
CCLK_NOSYNC
GSR Active
C2
C3
C4
7
DONE IN
F
DONE
I/O
C1, C2 or C3
Di
XC4000E/EX
XC5200/
CCLK_SYNC
Di+1
Di+1
GSR Active
Di
F
DONE
I/O
C1
U2
U2
U3
U3
U4
XC4000E/EX
XC5200/
UCLK_NOSYNC
U4
GSR Active
U2
U3
U4
DONE IN
F
DONE
I/O
C1
U2
XC4000E/EX
XC5200/
Di
Di+1
Di+2
Di+2
UCLK_SYNC
GSR Active
Di Di+1
Synchronization
Uncertainty
UCLK Period
X6700
Figure 25: Start-up Timing
November 5, 1998 (Version 5.2)
7-109
ETC [ ETC ]
