R
XC5200 Series Field Programmable Gate Arrays
Master Serial mode generates CCLK and receives the con-
figuration data in serial form from a Xilinx serial-configura-
tion PROM.
Multi-Family Daisy Chain
All Xilinx FPGAs of the XC2000, XC3000, XC4000, and
XC5200 Series use a compatible bitstream format and can,
therefore, be connected in a daisy chain in an arbitrary
sequence. There is, however, one limitation. If the chain
contains XC5200-Series devices, the master normally can-
not be an XC2000 or XC3000 device.
CCLK speed is selectable as 1 MHz (default), 6 MHz, or 12
MHz. Configuration always starts at the default slow fre-
quency, then can switch to the higher frequency during the
first frame. Frequency tolerance is -50% to +50%.
The reason for this rule is shown in Figure 25 on page 109.
Since all devices in the chain store the same length count
value and generate or receive one common sequence of
CCLK pulses, they all recognize length-count match on the
same CCLK edge, as indicated on the left edge of
Figure 25. The master device then generates additional
CCLK pulses until it reaches its finish point F. The different
families generate or require different numbers of additional
CCLK pulses until they reach F. Not reaching F means that
the device does not really finish its configuration, although
DONE may have gone High, the outputs became active,
and the internal reset was released. For the
XC5200-Series device, not reaching F means that read-
back cannot be initiated and most boundary scan instruc-
tions cannot be used.
Peripheral Modes
The two Peripheral modes accept byte-wide data from a
bus. A RDY/BUSY status is available as a handshake sig-
nal. In Asynchronous Peripheral mode, the internal oscilla-
tor generates a CCLK burst signal that serializes the
byte-wide data. CCLK can also drive slave devices. In the
synchronous mode, an externally supplied clock input to
CCLK serializes the data.
Slave Serial Mode
In Slave Serial mode, the FPGA receives serial configura-
tion data on the rising edge of CCLK and, after loading its
configuration, passes additional data out, resynchronized
on the next falling edge of CCLK.
Multiple slave devices with identical configurations can be
wired with parallel DIN inputs. In this way, multiple devices
can be configured simultaneously.
The user has some control over the relative timing of these
events and can, therefore, make sure that they occur at the
proper time and the finish point F is reached. Timing is con-
trolled using options in the bitstream generation software.
7
Serial Daisy Chain
XC5200 devices always have the same number of CCLKs
in the power up delay, independent of the configuration
mode, unlike the XC3000/XC4000 Series devices. To guar-
antee all devices in a daisy chain have finished the
power-up delay, tie the INIT pins together, as shown in
Figure 27.
Multiple devices with different configurations can be con-
nected together in a “daisy chain,” and a single combined
bitstream used to configure the chain of slave devices.
To configure a daisy chain of devices, wire the CCLK pins
of all devices in parallel, as shown in Figure 28 on page
114. Connect the DOUT of each device to the DIN of the
next. The lead or master FPGA and following slaves each
passes resynchronized configuration data coming from a
single source. The header data, including the length count,
is passed through and is captured by each FPGA when it
recognizes the 0010 preamble. Following the length-count
data, each FPGA outputs a High on DOUT until it has
received its required number of data frames.
XC3000 Master with an XC5200-Series Slave
Some designers want to use an XC3000 lead device in
peripheral mode and have the I/O pins of the
XC5200-Series devices all available for user I/O. Figure 22
provides a solution for that case.
This solution requires one CLB, one IOB and pin, and an
internal oscillator with a frequency of up to 5 MHz as a
clock source. The XC3000 master device must be config-
ured with late Internal Reset, which is the default option.
After an FPGA has received its configuration data, it
passes on any additional frame start bits and configuration
data on DOUT. When the total number of configuration
clocks applied after memory initialization equals the value
of the 24-bit length count, the FPGAs begin the start-up
sequence and become operational together. FPGA I/O are
normally released two CCLK cycles after the last configura-
tion bit is received. Figure 25 on page 109 shows the
start-up timing for an XC5200-Series device.
One CLB and one IOB in the lead XC3000-family device
are used to generate the additional CCLK pulse required by
the XC5200-Series devices.
When the lead device
removes the internal RESET signal, the 2-bit shift register
responds to its clock input and generates an active Low
output signal for the duration of the subsequent clock
period. An external connection between this output and
CCLK thus creates the extra CCLK pulse.
The daisy-chained bitstream is not simply a concatenation
of the individual bitstreams. The PROM file formatter must
be used to combine the bitstreams for a daisy-chained con-
figuration.
November 5, 1998 (Version 5.2)
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