X51638
SPI SERIAL MEMORY
Write Enable Latch
The device contains a Write Enable Latch. This latch
must be SET before a Write Operation is initiated. The
WREN instruction will set the latch and the WRDI instruc-
tion will reset the latch (Figure 3). This latch is automati-
cally reset upon a power-up condition and after the
completion of a valid Write Cycle.
The memory portion of the device is a CMOS Serial
EEPROM array with Xicor’s Block LockTM Protection. The
array is internally organized as x 8. The device features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
The device utilizes Xicor’s proprietary Direct WriteTM cell,
providing a minimum endurance of 100,000 cycles and a
minimum data retention of 100 years.
Status Register
The RDSR instruction provides access to the Status Reg-
ister. The Status Register may be read at any time, even
during a Write Cycle. The Status Register is formatted as
follows:
The device is designed to interface directly with the syn-
chronous Serial Peripheral Interface (SPI) of many popu-
lar microcontroller families. It contains an 8-bit instruction
register that is accessed via the SI input, with data being
clocked in on the rising edge of SCK. CS must be LOW
during the entire operation.
7
6
5
4
3
2
1
0
WPEN FLB WD1 WD0 BL1 BL0 WEL WIP
All instructions (Table 1), addresses and data are trans-
ferred MSB first. Data input on the SI line is latched on the
first rising edge of SCK after CS goes LOW. Data is out-
put on the SO line by the falling edge of SCK. SCK is
static, allowing the user to stop the clock and then start it
again to resume operations where left off.
The Write-In-Progress (WIP) bit is a volatile, read only bit
and indicates whether the device is busy with an internal
nonvolatile write operation. The WIP bit is read using the
RDSR instruction. When set to a “1”, a nonvolatile write
operation is in progress. When set to a “0”, no write is in
progress.
Table 1. Instruction Set
Instruction Name Instruction Format*
Operation
WREN
SFLB
0000 0110
0000 0000
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Set the Write Enable Latch (Enable Write Operations)
Set Flag Bit
WRDI/RFLB
RSDR
Reset the Write Enable Latch/Reset Flag Bit
Read Status Register
WRSR
Write Status Register(Watchdog,BlockLock,WPEN & Flag Bits)
Read Data from Memory Array Beginning at Selected Address
Write Data to Memory Array Beginning at Selected Address
READ
WRITE
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
Table 2. Block Protect Matrix
STATUS
REGISTER
DEVICE
PIN
STATUS
REGISTER
WREN CMD
BLOCK
BLOCK
WPEN, BL0, BL1
WD0, WD1
Protected
PROTECTED
BLOCK
UNPROTECTED
BLOCK
WEL
WPEN
WP#
0
1
1
1
X
1
0
X
X
0
X
1
Protected
Protected
Protected
Protected
Protected
Writable
Writable
Writable
Protected
Writable
Writable
5
ETC [ ETC ]
