X51638
The Write Enable Latch (WEL) bit indicates the Status of
the Write Enable Latch. When WEL=1, the latch is set
HIGH and when WEL=0 the latch is reset LOW. The WEL
bit is a volatile, read only bit. It can be set by the WREN
instruction and can be reset by the WRDS instruction.
Status Register Bits
Watchdog Time-out
(Typical)
WD1
WD0
0
0
1
1
0
1
0
1
1.4 Seconds
600 Milliseconds
400 Milliseconds
Disabled
The Block Lock bits, BL0 and BL1, set the level of Block
LockTM Protection. These nonvolatile bits are pro-
grammed using the WRSR instruction and allow the user
to protect one quarter, one half, all or none of the
EEPROM array. Any portion of the array that is Block Lock
Protected can be read but not written. It will remain pro-
tected until the BL bits are altered to disable Block Lock
Protection of that portion of memory.
The FLAG bit shows the status of a volatile latch that can
be set and reset by the system using the SFLB and RFLB
instructions. The Flag bit is automatically reset upon
power up. This flag can be used by the system to deter-
mine whether a reset occurs as a result of a watchdog
time-out or power failure.
Status
Register Bits
Array Addresses Protected
X516x
BL1
BL0
The nonvolatile WPEN bit is programmed using the
WRSR instruction. This bit works in conjunction with the
WP pin to provide an In-Circuit Programmable ROM func-
tion (Table 2). WP is LOW and WPEN bit programmed
HIGH disables all Status Register Write Operations.
0
0
1
1
0
1
0
1
None
$0600–$07FF
$0400–$07FF
$0000–$07FF
In Circuit Programmable ROM Mode
The Watchdog Timer bits, WD0 and WD1, select the
Watchdog Time-out Period. These nonvolatile bits are
programmed with the WRSR instruction.
This mechanism protects the Block Lock and Watchdog
bits from inadvertant corruption.
In the locked state (Programmable ROM Mode) the WP
pin is LOW and the nonvolatile bit WPEN is “1”.This mode
disables nonvolatile writes to the device’s Status Register.
Figure 5. Read EEPROM Array Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
SCK
SI
INSTRUCTION
16 BIT ADDRESS
15 14 13
3
2
1
0
DATA OUT
HIGH IMPEDANCE
7
6
5
4
3
2
1
0
SO
MSB
6
ETC [ ETC ]
