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X51638S8-1.8 参数 Datasheet PDF下载

X51638S8-1.8图片预览
型号: X51638S8-1.8
PDF下载: 下载PDF文件 查看货源
内容描述: SPI串行EEPROM与监控功能\n [SPI Serial EEPROM with Supervisory Features ]
分类和应用: 光电二极管监控可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 21 页 / 102 K
品牌: ETC [ ETC ]
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X51638  
PRINCIPLES OF OPERATION  
To set the new V  
voltage, apply the desired V  
TRIP TRIP  
threshold to the Vcc pin and tie the CS/WDI pin and the  
WP pin HIGH. RESET and SO pins are left unconnected.  
Then apply the programming voltage Vp to both SCK and  
SI and pulse CS/WDI LOW then HIGH. Remove Vp and  
the sequence is complete.  
POWER ON RESET  
Application of power to the X51638 activates a Power On  
Reset Circuit. This circuit goes active at V  
sense level  
CC  
(V  
) and pulls the RESET pin LOW. This signal pre-  
TRIP  
vents the system microprocessor from starting to operate  
with insufficient voltage or prior to stabilization of the oscil-  
Figure 1. Set V  
Voltage  
TRIP  
lator. When Vcc exceeds the device V  
value for  
TRIP  
800ms (nominal) the circuit releases RESET, allowing the  
processor to begin executing code.  
CS  
Vp  
SCK  
LOW VOLTAGE MONITORING  
During operation, the X51638 monitors the V level and  
asserts RESET if supply voltage falls below a preset mini-  
CC  
Vp  
SI  
mum V  
. The RESET signal prevents the microproces-  
TRIP  
sor from operating in a power fail or brownout condition.  
The RESET signal remains active until the voltage drops  
below 1V. It also remains active until Vcc returns and  
Resetting the V  
Voltage  
TRIP  
exceeds V  
for 800ms.  
TRIP  
This procedure sets the V  
to a “native” voltage level.  
TRIP  
For example, if the current V  
is 4.4V and the V  
is  
TRIP  
TRIP  
WATCHDOG TIMER  
reset, the new V  
is something less than 1.7V. This  
TRIP  
The Watchdog Timer circuit monitors the microprocessor  
activity by monitoring the WDI input. The microprocessor  
must toggle the CS/WDI pin periodically to prevent a  
RESET signal. The CS/WDI pin must be toggled from  
HIGH to LOW prior to the expiration of the watchdog time-  
out period. The state of two nonvolatile control bits in the  
Status Register determine the watchdog timer period.The  
microprocessor can change these watchdog bits, or they  
may be “locked” by tying the WP pin LOW and setting the  
WPEN bit HIGH.  
procedure must be used to set the voltage to a lower  
value.  
To reset the V  
voltage, apply a voltage between 2.7  
TRIP  
and 5.5V to the Vcc pin. Tie the CS/WDI pin, the WP pin,  
AND THE SCK pin HIGH. RESET and SO pins are left  
unconnected. Then apply the programming voltage Vp to  
the SI pin ONLY and pulse CS/WDI LOW then HIGH.  
Remove Vp and the sequence is complete.  
Figure 2. Reset V  
Voltage  
TRIP  
VCC THRESHOLD RESET PROCEDURE  
The X51638 is offered with one of several standard Vcc  
CS  
threshold (V  
) voltages. This value will not change  
TRIP  
Vcc  
over normal operating and storage conditions. However,  
in applications where the standard V is not exactly  
SCK  
TRIP  
right, or for higher precision in the V  
X51638 threshold may be adjusted.  
value, the  
TRIP  
Vp  
SI  
Setting the V  
Voltage  
TRIP  
This procedure sets the V  
to a higher voltage value.  
TRIP  
For example, if the current V  
is 4.4V and the new  
TRIP  
V
is 4.6V, this procedure directly makes the change. If  
TRIP  
the new setting is lower than the current setting, then it is  
necessary to reset the trip point before setting the new  
value.  
3
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