欢迎访问ic37.com |
会员登录 免费注册
发布采购

X51638S8-1.8 参数 Datasheet PDF下载

X51638S8-1.8图片预览
型号: X51638S8-1.8
PDF下载: 下载PDF文件 查看货源
内容描述: SPI串行EEPROM与监控功能\n [SPI Serial EEPROM with Supervisory Features ]
分类和应用: 光电二极管监控可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 21 页 / 102 K
品牌: ETC [ ETC ]
 浏览型号X51638S8-1.8的Datasheet PDF文件第1页浏览型号X51638S8-1.8的Datasheet PDF文件第3页浏览型号X51638S8-1.8的Datasheet PDF文件第4页浏览型号X51638S8-1.8的Datasheet PDF文件第5页浏览型号X51638S8-1.8的Datasheet PDF文件第6页浏览型号X51638S8-1.8的Datasheet PDF文件第7页浏览型号X51638S8-1.8的Datasheet PDF文件第8页浏览型号X51638S8-1.8的Datasheet PDF文件第9页  
X51638  
PIN DESCRIPTION  
PIN  
PIN  
(SOIC/PDIP)  
TSSOP  
Name  
Function  
Chip Select Input. CS HIGH, deselects the device and the SO output pin  
is at a high impedance state. Unless a nonvolatile write cycle is underway,  
the device will be in the standby power mode. CS LOW enables the device,  
placing it in the active power mode. Prior to the start of any operation after  
power up, a HIGH to LOW transition on CS is required  
1
1
CS/WDI  
Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the  
Watchdog timer. The absence of a HIGH to LOW transition within the  
watchdog time-out period results in RESET going active.  
Serial Output. SO is a push/pull serial data output pin.A read cycle shifts data  
out on this pin.The falling edge of the serial clock (SCK) clocks the data out.  
2
5
2
8
SO  
SI  
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses,  
and memory data on this pin.The rising edge of the serial clock (SCK) latches  
the input data. Send all opcodes (Table 1), addresses and data MSB first.  
Serial Clock. The Serial Clock controls the serial bus timing for data input and  
output.The rising edge of SCK latches in the opcode, address, or data bits  
present on the SI pin.The falling edge of SCK changes the data output on the  
SO pin.  
6
3
9
6
SCK  
WP  
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN  
bit to “lock” the setting of the Watchdog Timer control and the memory write  
protect bits.  
V
4
8
7
Ground  
SS  
V
14  
Supply Voltage  
CC  
Reset Output. RESET is an active LOW open drain output which goes  
active whenever Vcc falls below the minimum Vcc sense level. It will  
remain active until Vcc rises above the minimum Vcc sense level for  
800ms. RESET goes active if the Watchdog Timer is enabled and CS  
remains either HIGH or LOW longer than the selectable Watchdog time-out  
period. A falling edge of CS will reset the Watchdog Timer. RESET goes  
active on power up at 1V and remains active for 800ms after the power  
supply stabilizes.  
7
13  
RESET  
NC  
3-5,10-12  
No internal connections  
PIN CONFIGURATION  
14-LEAD TSSOP  
X51638  
8-LEAD SOIC/PDIP  
X51638  
V
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
CS  
SO  
NC  
CC  
RESET  
NC  
V
1
2
3
4
8
7
6
5
CS  
SO  
WP  
CC  
RESET  
SCK  
SI  
NC  
NC  
WP  
NC  
NC  
V
SS  
SCK  
SI  
V
SS  
8
2
 复制成功!