Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
Channel 1--
ASCI Receive Register
Register addresses 08H and 09H hold the ASCI receive
data for channel 0 and channel 1, respectively.
Mnemonics TSR1
Address (09H)
1
Channel 0
Mnemonics TSR0 --
Address (08H)
2
7
6
5
4
3
1
0
--
--
--
-- --
-- --
--
2
7
6
5
4
3
1
0
ASCI Transmit Data
--
--
--
-- --
-- --
--
Figure 39. ASCI Receive Register Channel 1R
ASCI Transmit Data
Figure 38. ASCI Receive Register Channel 0
CSI/O CONTROL/STATUS REGISTER
(CNTR: I/O Address = 0AH). CNTR is used to monitor
CSI/O status, enable and disable the CSI/O, enable and
disable interrupt generation, and select the data clock
speed and source.
5
3
Bit
7
6
4
2
1
0
__
SS2
R/W
SS1
R/W
SS0
R/W
EF
R
EIE
RE
TE
R/W
R/W
R/W
Figure 40. CSI/O Control Register
EF: End Flag (bit 7). EF is set to 1 by the CSI/O to indicate
completion of an 8-bit data transmit or receive operation. If
EIE (End Interrupt Enable) bit = 1 when EF is set to 1, a
CPU interrupt request is generated. Program access of
TRDR only occurs if EF = 1. The CSI/O clears EF to 0
when TRDR is read or written. EF is cleared to 0 during
RESET and IOSTOP mode.
is input on the CKS pin. In either case, data is shifted in on
the RXS pin in synchronization with the (internal or exter-
nal) data clock. After receiving 8 bits of data, the CSI/O au-
tomatically clears RE to 0, EF is set to 1, and an interrupt
(if enabled by EIE = 1) is generated. RE and TE are never
both set to 1 at the same time. RE is cleared to 0 during
RESET and ISTOP mode.
EIE: End Interrupt Enable (bit 6). EIE is set to 1 to gen-
erate a CPU interrupt request. The interrupt request is in-
hibited if EIE is reset to 0. EIE is cleared to 0 during RE-
SET.
RE: Receive Enable (bit 5). A CSI/O receive operation is
started by setting RE to 1. When RE is set to 1, the data
clock is enabled. In internal clock mode, the data clock is
output from the CKS pin. In external clock mode, the clock
DS971800401
P R E L I M I N A R Y
1-43
ZILOG [ ZILOG, INC. ]
