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Z8S18020VSG 参数 Datasheet PDF下载

Z8S18020VSG图片预览
型号: Z8S18020VSG
PDF下载: 下载PDF文件 查看货源
内容描述: 两个链条链接的DMA通道 [Two Chain-Linked DMA Channels]
分类和应用: 微控制器和处理器外围集成电路微处理器时钟
文件页数/大小: 71 页 / 2080 K
品牌: ZILOG [ ZILOG, INC. ]
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$KVꢄꢇꢄ.0+1ꢆꢄThis bit controls the drive capability of certain  
external I/O pins of the Z8S180/Z8L180. When this bit is  
set to 1, the output drive capability of the following pins is  
reduced to 33 percent of the original drive capability:  
$KVꢄꢁꢄ.0%27%6.ꢆꢄThis bit controls the drive capability of  
the CPU Control pins. When this bit is set to 1, the output  
drive capability of the following pins is reduced to 33 per-  
cent of the original drive capability:  
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6Z5  
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94  
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6'56  
6'0&K  
%-5  
56  
$KVꢄꢂꢄ.0#&ꢃ&#6#ꢆꢄThis bit controls the drivecapability of  
the Address/Data bus output drivers. If this bit is set to 1,  
the output drive capability of the Address and Data bus out-  
puts is reduced to 33 percent of its original drive capability.  
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