Z8 Encore!® Motor Control Flash MCUs
Product Specification
44
Port A–C High Drive Enable Subregisters
The Port A–C High Drive Enable subregisters, shown in Table 21, are accessed through
the Port A-C Control registers by writing 04hto the Port A–C Address registers. Setting
the bits in the Port A–C High Drive Enable subregisters to 1 configures the specified port
pins for high current output drive operation. The Port A–C High Drive Enable subregisters
affect the pins directly and, as a result, alternate functions are also affected.
Table 21. Port A–C High Drive Enable Sub-Registers
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
PHDE7
PHDE6
PHDE5
PHDE4
PHDE3
PHDE2
PHDE1
PHDE0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
If 04H in Port A-C Address Register, accessible through the Port A-C Control Register
ADDR
Bit
Value
(H)
Description
Position
[7:0]
Port High Drive Enable
PHDE
0
1
The Port pin is configured for standard output current drive.
The Port pin is configured for high output current drive.
Port A–C Stop-Mode Recovery Source Enable Subregisters
The Port A–C Stop-Mode Recovery Source Enable subregisters, shown in Table 22, are
accessed through the Port A–C Control registers by writing 05hto the Port A-C Address
registers. Setting the bits in the Port A–C Stop-Mode Recovery Source Enable subregisters
to 1 configures the specified port pins as a Stop-Mode Recovery source. During STOP
mode, any logic transition on a port pin enabled as a Stop-Mode Recovery source initiates
Stop-Mode Recovery.
General-Purpose I/O
P R E L I M I N A R Y
PS024604-1005
ZILOG [ ZILOG, INC. ]
