Z8 Encore!® Motor Control Flash MCUs
Product Specification
40
Table 14. GPIO Port Registers and Subregisters
Port Register Mnemonic
PxADDR
Port Register Name
Port A–C Address Register—selects subregisters.
PxCTL
Port A–C Control Register—provides access to
subregisters.
PxIN
Port A–C Input Data Register.
Port A–C Output Data Register.
PxOUT
Port Subregister Mnemonic Port Register Name
PxDD
Data Direction
PxAF0
Alternate Function 0
PxAF1
Alternate Function 1—Ports A and B only.
Output Control (open-drain).
High Drive Enable.
PxOC
PxHDE
PxSMRE
PxPUE
PxIRQES
IRQPSEL
Stop-Mode Recovery Source Enable.
Pull-Up Enable.
Interrupt Edge Select—Ports A and C only.
Interrupt Port Select—Port A only.
Port A-C Address Registers
The Port A–C Address registers select the GPIO port functionality accessible through the
Port A–C Control registers. The Port A–C Address and Control registers combine to pro-
vide access to all GPIO port control. See Table 15.
Table 15. Port A–C GPIO Address Registers (PxADDR)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
PADDR[7:0]
00H
R/W
FD0H, FD4H, FD8H
ADDR
Table 16 lists the Port Control subregisters that are accessible via the Port A–C Control
registers.
General-Purpose I/O
P R E L I M I N A R Y
PS024604-1005
ZILOG [ ZILOG, INC. ]
