Z8FMC16100 Series Flash MCU
Product Specification
41
Table 16. Port Control Subregisters by Port Address
Port
Address
Port Control Subregisters
00h
No function; provides some protection against accidental port
reconfiguration.
01h
Data direction.
02h
Alternate Function 0
03h
Output Control (open-drain).
High Drive Enable.
04h
05h
Stop-mode recovery source enable.
Pull-up enable.
06h
07h
Alternate Function 1—ports A and B only.
Interrupt Edge Select - Port A and Port C only
Port Interrupt Select Register - Port A only
No Function
08h
09h
0Ah–FFh
Port A–C Control Registers
The Port A–C Control registers set the GPIO port operation. The value in the correspond-
ing Port A–C Address register determines the control subregisters accessible using the
Port A–C Control registers, shown in Table 17. The Port Control registers provide access
to all subregisters that configure GPIO port operation.
Table 17. Port A–C Control Registers (PxCTL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
PCTL
00H
R/W
FD1H, FD5H, FD9H
ADDR
Port A–C Data Direction Subregisters
The Port A–C Data Direction subregisters are accessed through the Port A–C Control reg-
isters by writing 01hto the Port A–C Address registers. See Table 18.
PS024604-1005
P R E L I M I N A R Y
Port A–C Control Registers
ZILOG [ ZILOG, INC. ]
