Z8FMC16100 Series Flash MCU
Product Specification
39
Table 13. Port Alternate Function Mapping (Continued)
Port
Pin
Mnemonic
PB2
AF0 AF1 Alternate Function Description
Port B PB2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
GPIO/Timer 0 input 2.
PB2INT
ANA2
GPIO/Timer 0 input 2—edge interrupt enabled.
ADC analog input 2.
T0IN2
PB1
Timer 0 input 2; dedicated input.
GPIO/Timer 0 input 1.
PB1
PB1INT
ANA1
GPIO/Timer 0 input 1—edge interrupt enabled.
ADC analog input 1.
Reserved; do not use.
PB0
PB0
GPIO/Timer 0 input 0.
PB0INT
ANA0
GPIO/Timer 0 input 0—edge interrupt enabled.
ADC analog input 0.
Reserved; do not use.
Port C PC0
PC0
GPIO.
Reserved; do not use.
T0OUT
Timer 0 output.
Reserved; do not use.
GPIO Interrupts
Many of the GPIO port pins can be used as interrupt sources. The Port A[7:0] pins can be
configured to generate an interrupt request on either the rising edge or falling edge of the
pin input signal. The Port B[3:0] pins can be configured to generate an interrupt request on
both the rising and falling edges of the pin input signal. For Port A, the GPIO interrupt
edge selection is controlled by the Interrupt Edge Select subregister. Enabling and dis-
abling of the Port Interrupts is handled in the Interrupt Controller. Port B[3:0], with dual
edge interrupt capability, is selected by AF1, AF0. Refer to the Interrupt Controller chap-
ter on page 51 for more information.
GPIO Control Register Definitions
Four registers for each Port provide access to GPIO control, input data, and output data.
Table 14 lists these Port registers. Use the Port A–C Address and Control registers
together to provide access to subregisters for Port configuration and control.
PS024604-1005
P R E L I M I N A R Y
GPIO Interrupts
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