Z8 Encore!® Motor Control Flash MCUs
Product Specification
188
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2
Table 95. I C Baud Rate High Byte Register (I2CBRH)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
BRH
FFH
R/W
F53H
ADDR
BRH = I2C Baud Rate High Byte
Most significant byte, BRG[15:8], of the I2C Baud Rate Generator’s reload value.
If the DIAGbit in the I2C Mode Register is set to 1, a read of the I2CBRH register returns
Note:
the current value of the I2C Baud Rate Counter[15:8].
2
Table 96. I C Baud Rate Low Byte Register (I2CBRL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
BRL
FFH
R/W
F54H
ADDR
BRL = I2C Baud Rate Low Byte
Least significant byte, BRG[7:0], of the I2C Baud Rate Generator’s reload value.
If the DIAGbit in the I2C Mode Register is set to 1, a read of the I2CBRL register returns
Note:
the current value of the I2C Baud Rate Counter[7:0]
I2C State Register
The read-only I2C State Register provides information about the state of the I2C bus and
the I2C bus controller.
When the DIAGbit of the I2C Mode Register is cleared, this register provides information
on the internal state of the I2C controller and I2C bus, as shown in Table 97. A more
detailed discussion of each bit follows this table.
When the DIAGbit of the I2C Mode Register is set, this register returns the value of the
I2C controller state machine, as shown in Table 98, which follows on page 190.
I2C Master/Slave Controller
P R E L I M I N A R Y
PS024604-1005
ZILOG [ ZILOG, INC. ]
