Z8 Encore!® Motor Control Flash MCUs
Product Specification
186
SPRS—Stop/Restart Condition Interrupt
This bit is set when the I2C Controller is enabled in Slave mode and detects a STOP or
RESTART condition during a transaction directed to this slave. This bit clears when the
I2CISTAT register is read. Read the RSTRbit of the I2CSTATE register to determine
whether the interrupt was caused by a STOP or RESTART condition.
NCKI—NAK Interrupt
In Master mode, this bit is set when a Not Acknowledge condition is received or sent and
neither the STARTnor the STOPbit is active. In Master mode, this bit can only be cleared
by setting the STARTor STOPbits.
In Slave mode, this bit is set when a Not Acknowledge condition is received (Master read-
ing data from Slave), indicating the Master is finished reading. A STOP or RESTART con-
dition follows. In Slave mode this bit clears when the I2CISTAT register is read.
2
I C Control Register
The I2C Control Register, shown in Table 94, enables and configures I2C operation.
2
Table 94. I C Control Register (I2CCTL)
BITS
FIELD
RESET
R/W
7
IEN
6
5
4
3
TXI
2
NAK
1
0
START
STOP
BIRQ
FLUSH
FILTEN
0
0
0
0
0
0
0
0
R/W
R/W1
R/W1
R/W
R/W
R/W1
R/W
R/W
F52H
ADDR
NOTE: R/W1 - bit may be set (write 1) but not cleared.
IEN—I2C Enable
This bit enables the I2C Controller.
START—Send Start Condition
When set, this bit causes the I2C Controller (when configured as the Master) to send the
Start condition. Once asserted, it is cleared by the I2C Controller after it sends the Start
condition or by deasserting the IENbit. If this bit is 1, it cannot be cleared by writing to
the bit. After this bit is set, the START condition is sent if there is data in the I2CDATA or
I2CSHIFT register. If there is no data in one of these registers, the I2C Controller waits
until data is loaded. If this bit is set while the I2C Controller is shifting out data, it gener-
ates a RESTART condition after the byte shifts and the acknowledge phase completes. If
the STOPbit is also set, it also waits until the STOP condition is sent before the START
condition.
If START is set while a slave mode transaction is underway to this device, the START bit
will be cleared and ARBLST bit in the Interrupt Status register will be set.
I2C Master/Slave Controller
P R E L I M I N A R Y
PS024604-1005
ZILOG [ ZILOG, INC. ]
