Z8FMC16100 Series Flash MCU
Product Specification
191
Table 99. I2CSTATE_H (Continued)
State
Encoding
State Name
State Description
1100
1101
1110
Master Transmit Data 9 substates, one for each data bit and one for the Acknowledge.
Master Receive Data 9 substates, one for each data bit and one for the Acknowledge.
Master Transmit Addr1 Master sending first address byte (7- and 10-bit addressing)
9 substates, one for each address bit and one for the
Acknowledge.
1111
Master Transmit Addr2 Master sending second address byte (10-bit addressing)
9 substates, one for each address bit and one for the
Acknowledge.
Table 100. I2CSTATE_L
Substate
State
I2CSTATE_H I2CSTATE_L Substate Name
State Description
0000–0100
0110–0111
0101
0000
0000
—
—
There are no substates for these I2CSTATE_H
values.
There are no substates for these I2CSTATE_H
values.
0000
0001
Master Start
Initiating a new transaction
Master Restart
Master is ending one transaction and starting a
new one without letting the bus go idle.
1000–1111
0111
0110
0101
0100
0011
0010
0001
0000
1000
send/receive bit 7
send/receive bit 6
send/receive bit 5
send/receive bit 4
send/receive bit 3
send/receive bit 2
send/receive bit 1
send/receive bit 0
Sending/Receiving most significant bit
Sending/Receiving least significant bit
Sending/Receiving Acknowledge
send/receive
Acknowledge
PS024604-1005
P R E L I M I N A R Y
I2C State Register
ZILOG [ ZILOG, INC. ]
