Z8 Encore!® Motor Control Flash MCUs
Product Specification
184
12. The software responds to the NAKinterrupt by clearing the TXIbit in the I2CCTL
Register and by asserting the FLUSHbit of the I2CCTL Register.
13. When the master has completed the Acknowledge cycle of the last transfer, it asserts a
STOPor RESTARTcondition on the bus.
14. The slave I2C controller asserts the STOP/RESTARTinterrupt (sets the SPRS bit in the
I2CISTAT Register).
15. The software responds to the STOPinterrupt by reading the I2CISTAT Register and
clearing the SPRSbit.
2
I C Data Register
The I2C Data Register, shown in Table 92, contains the data that is to be loaded into the
Shift Register to transmit onto the I2C bus. This register also contains data that is loaded
from the Shift Register after it is received from the I2C bus. The I2C Shift Register is not
accessible in the Register File address space, but is used only to buffer incoming and out-
going data.
Writes by the software to the I2CDATA Register are blocked if a slave Write transaction is
underway (the I2C controller is in SLAVE mode, and data is being received).
2
Table 92. I C Data Register (I2CDATA)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
DATA
0
R/W
F50H
ADDR
I2C Interrupt Status Register
The read-only I2C Interrupt Status Register, shown in Table 93, indicates the cause of any
current I2C interrupt and provides status of the I2C controller. When an interrupt occurs,
one or more of the TDRE, RDRF, SAM, ARBLST, SPRSor NCKIbits is set. The GCAand
RDbits do not generate an interrupt but rather provide status associated with the
SAMbit interrupt.
I2C Master/Slave Controller
P R E L I M I N A R Y
PS024604-1005
ZILOG [ ZILOG, INC. ]
