Z8 Encore!® Motor Control Flash MCUs
Product Specification
190
2
Table 98. I C State Register (I2CSTATE) - Description when DIAG = 1
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
I2CSTATE_H
I2CSTATE_L
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
F55H
ADDR
I2CSTATE_H—I2C State
This field defines the current state of the I2C Controller. It is the most significant nibble of
the internal state machine. Table 99 defines the states for this field.
2
I2CSTATE_L—Least significant nibble of the I C state machine. This field defines the
substates for the states defined by I2CSTATE_H. Table 100 defines the values for this
field.
Table 99. I2CSTATE_H
State
Encoding
State Name
Idle
State Description
2
2
0000
0001
0010
0011
I C bus is idle or I C controller is disabled.
2
Slave Start
Slave Bystander
Slave Wait
I C controller has received a START condition.
Address did not match; ignore remainder of transaction.
Waiting for STOP or RESTART condition after sending a Not
Acknowledge instruction.
0100
0101
0110
0111
Master Stop2
Master Start/Restart
Master Stop1
Master Wait
Master completing STOP condition (SCL = 1, SDA = 1).
MASTER mode sending START condition (SCL = 1, SDA = 0).
Master initiating STOP condition (SCL = 1, SDA = 0).
Master received a Not Acknowledge instruction, waiting for
software to assert STOP or START control bits.
1000
1001
1010
Slave Transmit Data
Slave Receive Data
9 substates, one for each data bit and one for the Acknowledge.
9 substates, one for each data bit and one for the Acknowledge.
Slave Receive Addr1 Slave receiving first address byte (7- and 10-bit addressing)
9 substates, one for each address bit and one for the
Acknowledge.
1011
Slave Receive Addr2 Slave Receiving second address byte (10-bit addressing)
9 substates, one for each address bit and one for the
Acknowledge.
I2C Master/Slave Controller
P R E L I M I N A R Y
PS024604-1005
ZILOG [ ZILOG, INC. ]
