Z8FMC16100 Series Flash MCU
Product Specification
175
7. The I2C slave acknowledges the address by pulling the SDA signal Low during the
next high period of SCL.
If the slave does not acknowledge the address byte, the I2C controller sets the NCKI
bit in the I2C Status Register, sets the ACKVbit, and clears the ACKbit in the I2C State
Register. The software responds to the Not Acknowledge interrupt by setting the STOP
bit and clearing the TXIbit. The I2C controller flushes the Transmit Data Register,
sends a STOPcondition on the bus, and clears the STOPand NCKIbits. The transaction
is complete, and the following steps can be ignored.
8. The I2C controller shifts in the first byte of data from the I2C slave on the SDA signal.
9. The I2C controller asserts the receive interrupt.
10. The software responds by reading the I2C Data Register. If the next data byte is to be
the final byte, the software must set the NAKbit of the I2C Control Register.
11. The I2C controller sends a Not Acknowledge to the I2C slave if the next byte is the
final byte; otherwise, it sends an Acknowledge.
12. If there are more bytes to transfer, the I2C controller returns to Step 7.
13. A NAK interrupt (NCKIbit in I2CISTAT) is generated by the I2C controller.
14. The software responds by setting the STOPbit of the I2C Control Register.
15. A STOPcondition is sent to the I2C slave.
Master Read Transaction with a 10-Bit Address
Figure 31 illustrates the read transaction format for a 10-bit addressed slave.
S
Slave Address W=0 A Slave Address A S Slave Address R=1
1st Byte 2nd Byte 1st Byte
A
Data
A
Data A P
Figure 31. Data Transfer Format—Master Read Transaction with a 10-Bit Address
The first seven bits transmitted in the first byte are 11110XX. The two XXbits are the two
most-significant bits of the 10-bit address. The lowest bit of the first byte transferred is the
write control bit.
The data transfer procedure for a Read operation to a 10-bit addressed slave is as follows:
1. The software initializes the MODEfield in the I2C Mode Register for MASTER/
SLAVE mode with 7- or 10-bit addressing (the I2C bus protocol allows the mixing of
slave address types). The MODEfield selects the address width for this mode when
addressed as a slave (but not for the remote slave). The software asserts the IENbit in
the I2C Control Register.
2. The software writes 11110b, followed by the two most-significant address bits and a
0 (write) to the I2C Data Register.
PS024604-1005
P R E L I M I N A R Y
Master Transactions
ZILOG [ ZILOG, INC. ]
