Z8FMC16100 Series Flash MCU
Product Specification
171
S
W
A
A
P
Start
Write
Acknowledge
Not Acknowledge
Stop
Master Write Transaction with a 7-Bit Address
Figure 28 illustrates the data transfer format from a master to a 7-bit addressed slave
S
Slave
W = 0
A
Data
A
Data
A
Data
A/A
P/S
Address
Figure 28. Data Transfer Format—Master Write Transaction with a 7-Bit Address
The procedure for a master transmit operation to a 7-bit addressed slave is as follows:
1. The software initializes the MODEfield in the I2C Mode Register for MASTER/
SLAVE mode with either a 7- or 10-bit slave address. The MODEfield selects the
address width for this mode when addressed as a slave (but not for the remote slave).
The software asserts the IENbit in the I2C Control Register.
2. The software asserts the TXIbit of the I2C Control Register to enable transmit inter-
rupts.
3. The I2C interrupt asserts, because the I2C Data Register is empty.
4. The software responds to the TDREbit by writing a 7-bit slave address plus the Write
bit (which is cleared to 0) to the I2C Data Register.
5. The software sets the STARTbit of the I2C Control Register.
6. The I2C controller sends a STARTcondition to the I2C slave.
7. The I2C controller loads the I2C Shift Register with the contents of the I2C Data Reg-
ister.
8. After one bit of the address has been shifted out by the SDA signal, the transmit inter-
rupt asserts.
9. The software responds by writing the transmit data into the I2C Data Register.
10. The I2C controller shifts the remainder of the address and the Write bit out via the
SDA signal.
11. The I2C slave sends an Acknowledge (by pulling the SDA signal Low) during the next
high period of SCL. The I2C controller sets the ACKbit in the I2C Status Register.
PS024604-1005
P R E L I M I N A R Y
Master Transactions
ZILOG [ ZILOG, INC. ]
